14a079c75SCarlo Caione /* 2f681c676SCarlo Caione * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 34a079c75SCarlo Caione * 44a079c75SCarlo Caione * SPDX-License-Identifier: BSD-3-Clause 54a079c75SCarlo Caione */ 64a079c75SCarlo Caione 74a079c75SCarlo Caione #ifndef PLATFORM_DEF_H 84a079c75SCarlo Caione #define PLATFORM_DEF_H 94a079c75SCarlo Caione 104a079c75SCarlo Caione #include <arch.h> 114a079c75SCarlo Caione #include <lib/utils_def.h> 124a079c75SCarlo Caione 134a079c75SCarlo Caione #include "../gxbb_def.h" 144a079c75SCarlo Caione 154a079c75SCarlo Caione #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 164a079c75SCarlo Caione #define PLATFORM_LINKER_ARCH aarch64 174a079c75SCarlo Caione 184a079c75SCarlo Caione /* Special value used to verify platform parameters from BL2 to BL31 */ 19*9158854aSCarlo Caione #define AML_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) 204a079c75SCarlo Caione 214a079c75SCarlo Caione #define PLATFORM_STACK_SIZE UL(0x1000) 224a079c75SCarlo Caione 234a079c75SCarlo Caione #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 244a079c75SCarlo Caione #define PLATFORM_CLUSTER_COUNT U(1) 254a079c75SCarlo Caione #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 264a079c75SCarlo Caione #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT 274a079c75SCarlo Caione 28f681c676SCarlo Caione #define AML_PRIMARY_CPU U(0) 294a079c75SCarlo Caione 304a079c75SCarlo Caione #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 314a079c75SCarlo Caione #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 324a079c75SCarlo Caione PLATFORM_CORE_COUNT) 334a079c75SCarlo Caione 344a079c75SCarlo Caione #define PLAT_MAX_RET_STATE U(1) 354a079c75SCarlo Caione #define PLAT_MAX_OFF_STATE U(2) 364a079c75SCarlo Caione 374a079c75SCarlo Caione /* Local power state for power domains in Run state. */ 384a079c75SCarlo Caione #define PLAT_LOCAL_STATE_RUN U(0) 394a079c75SCarlo Caione /* Local power state for retention. Valid only for CPU power domains */ 404a079c75SCarlo Caione #define PLAT_LOCAL_STATE_RET U(1) 414a079c75SCarlo Caione /* Local power state for power-down. Valid for CPU and cluster power domains. */ 424a079c75SCarlo Caione #define PLAT_LOCAL_STATE_OFF U(2) 434a079c75SCarlo Caione 444a079c75SCarlo Caione /* 454a079c75SCarlo Caione * Macros used to parse state information from State-ID if it is using the 464a079c75SCarlo Caione * recommended encoding for State-ID. 474a079c75SCarlo Caione */ 484a079c75SCarlo Caione #define PLAT_LOCAL_PSTATE_WIDTH U(4) 494a079c75SCarlo Caione #define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1) 504a079c75SCarlo Caione 514a079c75SCarlo Caione /* 524a079c75SCarlo Caione * Some data must be aligned on the biggest cache line size in the platform. 534a079c75SCarlo Caione * This is known only to the platform as it might have a combination of 544a079c75SCarlo Caione * integrated and external caches. 554a079c75SCarlo Caione */ 564a079c75SCarlo Caione #define CACHE_WRITEBACK_SHIFT U(6) 574a079c75SCarlo Caione #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 584a079c75SCarlo Caione 594a079c75SCarlo Caione /* Memory-related defines */ 604a079c75SCarlo Caione #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 614a079c75SCarlo Caione #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 624a079c75SCarlo Caione 634a079c75SCarlo Caione #define MAX_MMAP_REGIONS 12 644a079c75SCarlo Caione #define MAX_XLAT_TABLES 5 654a079c75SCarlo Caione 664a079c75SCarlo Caione #endif /* PLATFORM_DEF_H */ 67