1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/bl_common.h> 9 #include <common/interrupt_props.h> 10 #include <drivers/arm/gicv2.h> 11 #include <lib/xlat_tables/xlat_mmu_helpers.h> 12 #include <plat/common/platform.h> 13 #include <platform_def.h> 14 15 #include "aml_private.h" 16 17 /* 18 * Placeholder variables for copying the arguments that have been passed to 19 * BL31 from BL2. 20 */ 21 static entry_point_info_t bl33_image_ep_info; 22 23 /******************************************************************************* 24 * Return a pointer to the 'entry_point_info' structure of the next image for 25 * the security state specified. BL33 corresponds to the non-secure image type 26 * while BL32 corresponds to the secure image type. A NULL pointer is returned 27 * if the image does not exist. 28 ******************************************************************************/ 29 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 30 { 31 entry_point_info_t *next_image_info; 32 33 assert(type == NON_SECURE); 34 35 next_image_info = &bl33_image_ep_info; 36 37 /* None of the images can have 0x0 as the entrypoint. */ 38 if (next_image_info->pc != 0U) { 39 return next_image_info; 40 } else { 41 return NULL; 42 } 43 } 44 45 /******************************************************************************* 46 * Perform any BL31 early platform setup. Here is an opportunity to copy 47 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before 48 * they are lost (potentially). This needs to be done before the MMU is 49 * initialized so that the memory layout can be used while creating page 50 * tables. BL2 has flushed this information to memory, so we are guaranteed 51 * to pick up good data. 52 ******************************************************************************/ 53 struct gxbb_bl31_param { 54 param_header_t h; 55 image_info_t *bl31_image_info; 56 entry_point_info_t *bl32_ep_info; 57 image_info_t *bl32_image_info; 58 entry_point_info_t *bl33_ep_info; 59 image_info_t *bl33_image_info; 60 }; 61 62 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 63 u_register_t arg2, u_register_t arg3) 64 { 65 struct gxbb_bl31_param *from_bl2; 66 67 /* Initialize the console to provide early debug support */ 68 aml_console_init(); 69 70 /* 71 * In debug builds, we pass a special value in 'arg1' to verify platform 72 * parameters from BL2 to BL31. In release builds it's not used. 73 */ 74 assert(arg1 == AML_BL31_PLAT_PARAM_VAL); 75 76 /* Check that params passed from BL2 are not NULL. */ 77 from_bl2 = (struct gxbb_bl31_param *) arg0; 78 79 /* Check params passed from BL2 are not NULL. */ 80 assert(from_bl2 != NULL); 81 assert(from_bl2->h.type == PARAM_BL31); 82 assert(from_bl2->h.version >= VERSION_1); 83 84 /* 85 * Copy BL33 entry point information. It is stored in Secure RAM, in 86 * BL2's address space. 87 */ 88 bl33_image_ep_info = *from_bl2->bl33_ep_info; 89 90 if (bl33_image_ep_info.pc == 0U) { 91 ERROR("BL31: BL33 entrypoint not obtained from BL2\n"); 92 panic(); 93 } 94 } 95 96 void bl31_plat_arch_setup(void) 97 { 98 aml_setup_page_tables(); 99 100 enable_mmu_el3(0); 101 } 102 103 /******************************************************************************* 104 * GICv2 driver setup information 105 ******************************************************************************/ 106 static const interrupt_prop_t gxbb_interrupt_props[] = { 107 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, 108 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 109 INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, 110 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 111 INTR_PROP_DESC(IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, 112 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 113 INTR_PROP_DESC(IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, 114 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 115 INTR_PROP_DESC(IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, 116 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 117 INTR_PROP_DESC(IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, 118 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 119 INTR_PROP_DESC(IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, 120 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 121 INTR_PROP_DESC(IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, 122 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 123 INTR_PROP_DESC(IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, 124 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 125 }; 126 127 static const gicv2_driver_data_t gxbb_gic_data = { 128 .gicd_base = AML_GICD_BASE, 129 .gicc_base = AML_GICC_BASE, 130 .interrupt_props = gxbb_interrupt_props, 131 .interrupt_props_num = ARRAY_SIZE(gxbb_interrupt_props), 132 }; 133 134 void bl31_platform_setup(void) 135 { 136 aml_mhu_secure_init(); 137 138 gicv2_driver_init(&gxbb_gic_data); 139 gicv2_distif_init(); 140 gicv2_pcpu_distif_init(); 141 gicv2_cpuif_enable(); 142 143 aml_thermal_unknown(); 144 } 145