1*cdb8c52fSCarlo Caione# 2*cdb8c52fSCarlo Caione# Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*cdb8c52fSCarlo Caione# 4*cdb8c52fSCarlo Caione# SPDX-License-Identifier: BSD-3-Clause 5*cdb8c52fSCarlo Caione# 6*cdb8c52fSCarlo Caione 7*cdb8c52fSCarlo Caioneinclude lib/xlat_tables_v2/xlat_tables.mk 8*cdb8c52fSCarlo Caione 9*cdb8c52fSCarlo CaioneAML_PLAT := plat/amlogic 10*cdb8c52fSCarlo CaioneAML_PLAT_SOC := ${AML_PLAT}/${PLAT} 11*cdb8c52fSCarlo CaioneAML_PLAT_COMMON := ${AML_PLAT}/common 12*cdb8c52fSCarlo Caione 13*cdb8c52fSCarlo CaioneDOIMAGEPATH ?= tools/amlogic 14*cdb8c52fSCarlo CaioneDOIMAGETOOL ?= ${DOIMAGEPATH}/doimage 15*cdb8c52fSCarlo Caione 16*cdb8c52fSCarlo CaionePLAT_INCLUDES := -Iinclude/drivers/amlogic/ \ 17*cdb8c52fSCarlo Caione -I${AML_PLAT_SOC}/include \ 18*cdb8c52fSCarlo Caione -I${AML_PLAT_COMMON}/include 19*cdb8c52fSCarlo Caione 20*cdb8c52fSCarlo CaioneGIC_SOURCES := drivers/arm/gic/common/gic_common.c \ 21*cdb8c52fSCarlo Caione drivers/arm/gic/v2/gicv2_main.c \ 22*cdb8c52fSCarlo Caione drivers/arm/gic/v2/gicv2_helpers.c \ 23*cdb8c52fSCarlo Caione plat/common/plat_gicv2.c 24*cdb8c52fSCarlo Caione 25*cdb8c52fSCarlo CaioneBL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 26*cdb8c52fSCarlo Caione plat/common/plat_psci_common.c \ 27*cdb8c52fSCarlo Caione drivers/amlogic/console/aarch64/meson_console.S \ 28*cdb8c52fSCarlo Caione ${AML_PLAT_SOC}/${PLAT}_bl31_setup.c \ 29*cdb8c52fSCarlo Caione ${AML_PLAT_SOC}/${PLAT}_pm.c \ 30*cdb8c52fSCarlo Caione ${AML_PLAT_SOC}/${PLAT}_common.c \ 31*cdb8c52fSCarlo Caione ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \ 32*cdb8c52fSCarlo Caione ${AML_PLAT_COMMON}/aml_efuse.c \ 33*cdb8c52fSCarlo Caione ${AML_PLAT_COMMON}/aml_mhu.c \ 34*cdb8c52fSCarlo Caione ${AML_PLAT_COMMON}/aml_scpi.c \ 35*cdb8c52fSCarlo Caione ${AML_PLAT_COMMON}/aml_sip_svc.c \ 36*cdb8c52fSCarlo Caione ${AML_PLAT_COMMON}/aml_thermal.c \ 37*cdb8c52fSCarlo Caione ${AML_PLAT_COMMON}/aml_topology.c \ 38*cdb8c52fSCarlo Caione ${AML_PLAT_COMMON}/aml_console.c \ 39*cdb8c52fSCarlo Caione drivers/amlogic/crypto/sha_dma.c \ 40*cdb8c52fSCarlo Caione ${XLAT_TABLES_LIB_SRCS} \ 41*cdb8c52fSCarlo Caione ${GIC_SOURCES} 42*cdb8c52fSCarlo Caione 43*cdb8c52fSCarlo Caione# Tune compiler for Cortex-A53 44*cdb8c52fSCarlo Caioneifeq ($(notdir $(CC)),armclang) 45*cdb8c52fSCarlo Caione TF_CFLAGS_aarch64 += -mcpu=cortex-a53 46*cdb8c52fSCarlo Caioneelse ifneq ($(findstring clang,$(notdir $(CC))),) 47*cdb8c52fSCarlo Caione TF_CFLAGS_aarch64 += -mcpu=cortex-a53 48*cdb8c52fSCarlo Caioneelse 49*cdb8c52fSCarlo Caione TF_CFLAGS_aarch64 += -mtune=cortex-a53 50*cdb8c52fSCarlo Caioneendif 51*cdb8c52fSCarlo Caione 52*cdb8c52fSCarlo Caione# Build config flags 53*cdb8c52fSCarlo Caione# ------------------ 54*cdb8c52fSCarlo Caione 55*cdb8c52fSCarlo Caione# Enable all errata workarounds for Cortex-A53 56*cdb8c52fSCarlo CaioneERRATA_A53_855873 := 1 57*cdb8c52fSCarlo CaioneERRATA_A53_819472 := 1 58*cdb8c52fSCarlo CaioneERRATA_A53_824069 := 1 59*cdb8c52fSCarlo CaioneERRATA_A53_827319 := 1 60*cdb8c52fSCarlo Caione 61*cdb8c52fSCarlo CaioneWORKAROUND_CVE_2017_5715 := 0 62*cdb8c52fSCarlo Caione 63*cdb8c52fSCarlo Caione# Have different sections for code and rodata 64*cdb8c52fSCarlo CaioneSEPARATE_CODE_AND_RODATA := 1 65*cdb8c52fSCarlo Caione 66*cdb8c52fSCarlo Caione# Use Coherent memory 67*cdb8c52fSCarlo CaioneUSE_COHERENT_MEM := 1 68*cdb8c52fSCarlo Caione 69*cdb8c52fSCarlo Caione# Verify build config 70*cdb8c52fSCarlo Caione# ------------------- 71*cdb8c52fSCarlo Caione 72*cdb8c52fSCarlo Caioneifneq (${RESET_TO_BL31}, 0) 73*cdb8c52fSCarlo Caione $(error Error: ${PLAT} needs RESET_TO_BL31=0) 74*cdb8c52fSCarlo Caioneendif 75*cdb8c52fSCarlo Caione 76*cdb8c52fSCarlo Caioneifeq (${ARCH},aarch32) 77*cdb8c52fSCarlo Caione $(error Error: AArch32 not supported on ${PLAT}) 78*cdb8c52fSCarlo Caioneendif 79*cdb8c52fSCarlo Caione 80*cdb8c52fSCarlo Caioneall: ${BUILD_PLAT}/bl31.img 81*cdb8c52fSCarlo Caionedistclean realclean clean: cleanimage 82*cdb8c52fSCarlo Caione 83*cdb8c52fSCarlo Caionecleanimage: 84*cdb8c52fSCarlo Caione ${Q}${MAKE} -C ${DOIMAGEPATH} clean 85*cdb8c52fSCarlo Caione 86*cdb8c52fSCarlo Caione${DOIMAGETOOL}: 87*cdb8c52fSCarlo Caione ${Q}${MAKE} -C ${DOIMAGEPATH} 88*cdb8c52fSCarlo Caione 89*cdb8c52fSCarlo Caione${BUILD_PLAT}/bl31.img: ${BUILD_PLAT}/bl31.bin ${DOIMAGETOOL} 90*cdb8c52fSCarlo Caione ${DOIMAGETOOL} ${BUILD_PLAT}/bl31.bin ${BUILD_PLAT}/bl31.img 91*cdb8c52fSCarlo Caione 92