1*40fac1abSCarlo Caione/* 2*40fac1abSCarlo Caione * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*40fac1abSCarlo Caione * 4*40fac1abSCarlo Caione * SPDX-License-Identifier: BSD-3-Clause 5*40fac1abSCarlo Caione */ 6*40fac1abSCarlo Caione 7*40fac1abSCarlo Caione#include <arch.h> 8*40fac1abSCarlo Caione#include <asm_macros.S> 9*40fac1abSCarlo Caione#include <assert_macros.S> 10*40fac1abSCarlo Caione#include <platform_def.h> 11*40fac1abSCarlo Caione 12*40fac1abSCarlo Caione .globl plat_crash_console_flush 13*40fac1abSCarlo Caione .globl plat_crash_console_init 14*40fac1abSCarlo Caione .globl plat_crash_console_putc 15*40fac1abSCarlo Caione .globl platform_mem_init 16*40fac1abSCarlo Caione .globl plat_is_my_cpu_primary 17*40fac1abSCarlo Caione .globl plat_my_core_pos 18*40fac1abSCarlo Caione .globl plat_reset_handler 19*40fac1abSCarlo Caione .globl plat_gxbb_calc_core_pos 20*40fac1abSCarlo Caione 21*40fac1abSCarlo Caione /* ----------------------------------------------------- 22*40fac1abSCarlo Caione * unsigned int plat_my_core_pos(void); 23*40fac1abSCarlo Caione * ----------------------------------------------------- 24*40fac1abSCarlo Caione */ 25*40fac1abSCarlo Caionefunc plat_my_core_pos 26*40fac1abSCarlo Caione mrs x0, mpidr_el1 27*40fac1abSCarlo Caione b plat_gxbb_calc_core_pos 28*40fac1abSCarlo Caioneendfunc plat_my_core_pos 29*40fac1abSCarlo Caione 30*40fac1abSCarlo Caione /* ----------------------------------------------------- 31*40fac1abSCarlo Caione * unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr); 32*40fac1abSCarlo Caione * ----------------------------------------------------- 33*40fac1abSCarlo Caione */ 34*40fac1abSCarlo Caionefunc plat_gxbb_calc_core_pos 35*40fac1abSCarlo Caione and x0, x0, #MPIDR_CPU_MASK 36*40fac1abSCarlo Caione ret 37*40fac1abSCarlo Caioneendfunc plat_gxbb_calc_core_pos 38*40fac1abSCarlo Caione 39*40fac1abSCarlo Caione /* ----------------------------------------------------- 40*40fac1abSCarlo Caione * unsigned int plat_is_my_cpu_primary(void); 41*40fac1abSCarlo Caione * ----------------------------------------------------- 42*40fac1abSCarlo Caione */ 43*40fac1abSCarlo Caionefunc plat_is_my_cpu_primary 44*40fac1abSCarlo Caione mrs x0, mpidr_el1 45*40fac1abSCarlo Caione and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 46*40fac1abSCarlo Caione cmp x0, #GXBB_PRIMARY_CPU 47*40fac1abSCarlo Caione cset w0, eq 48*40fac1abSCarlo Caione ret 49*40fac1abSCarlo Caioneendfunc plat_is_my_cpu_primary 50*40fac1abSCarlo Caione 51*40fac1abSCarlo Caione /* --------------------------------------------- 52*40fac1abSCarlo Caione * void platform_mem_init(void); 53*40fac1abSCarlo Caione * --------------------------------------------- 54*40fac1abSCarlo Caione */ 55*40fac1abSCarlo Caionefunc platform_mem_init 56*40fac1abSCarlo Caione ret 57*40fac1abSCarlo Caioneendfunc platform_mem_init 58*40fac1abSCarlo Caione 59*40fac1abSCarlo Caione /* --------------------------------------------- 60*40fac1abSCarlo Caione * int plat_crash_console_init(void) 61*40fac1abSCarlo Caione * --------------------------------------------- 62*40fac1abSCarlo Caione */ 63*40fac1abSCarlo Caionefunc plat_crash_console_init 64*40fac1abSCarlo Caione mov_imm x0, GXBB_UART0_AO_BASE 65*40fac1abSCarlo Caione mov_imm x1, GXBB_UART0_AO_CLK_IN_HZ 66*40fac1abSCarlo Caione mov_imm x2, GXBB_UART_BAUDRATE 67*40fac1abSCarlo Caione b console_meson_init 68*40fac1abSCarlo Caioneendfunc plat_crash_console_init 69*40fac1abSCarlo Caione 70*40fac1abSCarlo Caione /* --------------------------------------------- 71*40fac1abSCarlo Caione * int plat_crash_console_putc(int c) 72*40fac1abSCarlo Caione * Clobber list : x1, x2 73*40fac1abSCarlo Caione * --------------------------------------------- 74*40fac1abSCarlo Caione */ 75*40fac1abSCarlo Caionefunc plat_crash_console_putc 76*40fac1abSCarlo Caione mov_imm x1, GXBB_UART0_AO_BASE 77*40fac1abSCarlo Caione b console_meson_core_putc 78*40fac1abSCarlo Caioneendfunc plat_crash_console_putc 79*40fac1abSCarlo Caione 80*40fac1abSCarlo Caione /* --------------------------------------------- 81*40fac1abSCarlo Caione * int plat_crash_console_flush() 82*40fac1abSCarlo Caione * Out : return -1 on error else return 0. 83*40fac1abSCarlo Caione * Clobber list : x0, x1 84*40fac1abSCarlo Caione * --------------------------------------------- 85*40fac1abSCarlo Caione */ 86*40fac1abSCarlo Caionefunc plat_crash_console_flush 87*40fac1abSCarlo Caione mov_imm x0, GXBB_UART0_AO_BASE 88*40fac1abSCarlo Caione b console_meson_core_flush 89*40fac1abSCarlo Caioneendfunc plat_crash_console_flush 90*40fac1abSCarlo Caione 91*40fac1abSCarlo Caione /* --------------------------------------------- 92*40fac1abSCarlo Caione * void plat_reset_handler(void); 93*40fac1abSCarlo Caione * --------------------------------------------- 94*40fac1abSCarlo Caione */ 95*40fac1abSCarlo Caionefunc plat_reset_handler 96*40fac1abSCarlo Caione ret 97*40fac1abSCarlo Caioneendfunc plat_reset_handler 98