140fac1abSCarlo Caione/* 2*831b0e98SJimmy Brisson * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. 340fac1abSCarlo Caione * 440fac1abSCarlo Caione * SPDX-License-Identifier: BSD-3-Clause 540fac1abSCarlo Caione */ 640fac1abSCarlo Caione 740fac1abSCarlo Caione#include <arch.h> 840fac1abSCarlo Caione#include <asm_macros.S> 940fac1abSCarlo Caione#include <assert_macros.S> 1040fac1abSCarlo Caione#include <platform_def.h> 1140fac1abSCarlo Caione 1240fac1abSCarlo Caione .globl plat_crash_console_flush 1340fac1abSCarlo Caione .globl plat_crash_console_init 1440fac1abSCarlo Caione .globl plat_crash_console_putc 1540fac1abSCarlo Caione .globl platform_mem_init 1640fac1abSCarlo Caione .globl plat_is_my_cpu_primary 1740fac1abSCarlo Caione .globl plat_my_core_pos 1840fac1abSCarlo Caione .globl plat_reset_handler 19f681c676SCarlo Caione .globl plat_calc_core_pos 2040fac1abSCarlo Caione 2140fac1abSCarlo Caione /* ----------------------------------------------------- 2240fac1abSCarlo Caione * unsigned int plat_my_core_pos(void); 2340fac1abSCarlo Caione * ----------------------------------------------------- 2440fac1abSCarlo Caione */ 2540fac1abSCarlo Caionefunc plat_my_core_pos 2640fac1abSCarlo Caione mrs x0, mpidr_el1 27f681c676SCarlo Caione b plat_calc_core_pos 2840fac1abSCarlo Caioneendfunc plat_my_core_pos 2940fac1abSCarlo Caione 3040fac1abSCarlo Caione /* ----------------------------------------------------- 31f681c676SCarlo Caione * unsigned int plat_calc_core_pos(u_register_t mpidr); 3240fac1abSCarlo Caione * ----------------------------------------------------- 3340fac1abSCarlo Caione */ 34f681c676SCarlo Caionefunc plat_calc_core_pos 3540fac1abSCarlo Caione and x0, x0, #MPIDR_CPU_MASK 3640fac1abSCarlo Caione ret 37f681c676SCarlo Caioneendfunc plat_calc_core_pos 3840fac1abSCarlo Caione 3940fac1abSCarlo Caione /* ----------------------------------------------------- 4040fac1abSCarlo Caione * unsigned int plat_is_my_cpu_primary(void); 4140fac1abSCarlo Caione * ----------------------------------------------------- 4240fac1abSCarlo Caione */ 4340fac1abSCarlo Caionefunc plat_is_my_cpu_primary 4440fac1abSCarlo Caione mrs x0, mpidr_el1 4540fac1abSCarlo Caione and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 46f681c676SCarlo Caione cmp x0, #AML_PRIMARY_CPU 4740fac1abSCarlo Caione cset w0, eq 4840fac1abSCarlo Caione ret 4940fac1abSCarlo Caioneendfunc plat_is_my_cpu_primary 5040fac1abSCarlo Caione 5140fac1abSCarlo Caione /* --------------------------------------------- 5240fac1abSCarlo Caione * void platform_mem_init(void); 5340fac1abSCarlo Caione * --------------------------------------------- 5440fac1abSCarlo Caione */ 5540fac1abSCarlo Caionefunc platform_mem_init 5640fac1abSCarlo Caione ret 5740fac1abSCarlo Caioneendfunc platform_mem_init 5840fac1abSCarlo Caione 5940fac1abSCarlo Caione /* --------------------------------------------- 6040fac1abSCarlo Caione * int plat_crash_console_init(void) 6140fac1abSCarlo Caione * --------------------------------------------- 6240fac1abSCarlo Caione */ 6340fac1abSCarlo Caionefunc plat_crash_console_init 64f681c676SCarlo Caione mov_imm x0, AML_UART0_AO_BASE 65f681c676SCarlo Caione mov_imm x1, AML_UART0_AO_CLK_IN_HZ 66f681c676SCarlo Caione mov_imm x2, AML_UART_BAUDRATE 6740fac1abSCarlo Caione b console_meson_init 6840fac1abSCarlo Caioneendfunc plat_crash_console_init 6940fac1abSCarlo Caione 7040fac1abSCarlo Caione /* --------------------------------------------- 7140fac1abSCarlo Caione * int plat_crash_console_putc(int c) 7240fac1abSCarlo Caione * Clobber list : x1, x2 7340fac1abSCarlo Caione * --------------------------------------------- 7440fac1abSCarlo Caione */ 7540fac1abSCarlo Caionefunc plat_crash_console_putc 76f681c676SCarlo Caione mov_imm x1, AML_UART0_AO_BASE 7740fac1abSCarlo Caione b console_meson_core_putc 7840fac1abSCarlo Caioneendfunc plat_crash_console_putc 7940fac1abSCarlo Caione 8040fac1abSCarlo Caione /* --------------------------------------------- 81*831b0e98SJimmy Brisson * void plat_crash_console_flush() 82*831b0e98SJimmy Brisson * Out : void. 8340fac1abSCarlo Caione * Clobber list : x0, x1 8440fac1abSCarlo Caione * --------------------------------------------- 8540fac1abSCarlo Caione */ 8640fac1abSCarlo Caionefunc plat_crash_console_flush 87f681c676SCarlo Caione mov_imm x0, AML_UART0_AO_BASE 8840fac1abSCarlo Caione b console_meson_core_flush 8940fac1abSCarlo Caioneendfunc plat_crash_console_flush 9040fac1abSCarlo Caione 9140fac1abSCarlo Caione /* --------------------------------------------- 9240fac1abSCarlo Caione * void plat_reset_handler(void); 9340fac1abSCarlo Caione * --------------------------------------------- 9440fac1abSCarlo Caione */ 9540fac1abSCarlo Caionefunc plat_reset_handler 9640fac1abSCarlo Caione ret 9740fac1abSCarlo Caioneendfunc plat_reset_handler 98