1*afd241e7SCarlo Caione# 2*afd241e7SCarlo Caione# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3*afd241e7SCarlo Caione# 4*afd241e7SCarlo Caione# SPDX-License-Identifier: BSD-3-Clause 5*afd241e7SCarlo Caione# 6*afd241e7SCarlo Caione 7*afd241e7SCarlo Caioneinclude lib/xlat_tables_v2/xlat_tables.mk 8*afd241e7SCarlo Caione 9*afd241e7SCarlo CaioneAML_PLAT := plat/amlogic 10*afd241e7SCarlo CaioneAML_PLAT_SOC := ${AML_PLAT}/${PLAT} 11*afd241e7SCarlo CaioneAML_PLAT_COMMON := ${AML_PLAT}/common 12*afd241e7SCarlo Caione 13*afd241e7SCarlo CaioneDOIMAGEPATH ?= tools/amlogic 14*afd241e7SCarlo CaioneDOIMAGETOOL ?= ${DOIMAGEPATH}/doimage 15*afd241e7SCarlo Caione 16*afd241e7SCarlo CaionePLAT_INCLUDES := -Iinclude/drivers/amlogic/ \ 17*afd241e7SCarlo Caione -I${AML_PLAT_SOC}/include \ 18*afd241e7SCarlo Caione -I${AML_PLAT_COMMON}/include 19*afd241e7SCarlo Caione 20*afd241e7SCarlo CaioneGIC_SOURCES := drivers/arm/gic/common/gic_common.c \ 21*afd241e7SCarlo Caione drivers/arm/gic/v2/gicv2_main.c \ 22*afd241e7SCarlo Caione drivers/arm/gic/v2/gicv2_helpers.c \ 23*afd241e7SCarlo Caione plat/common/plat_gicv2.c 24*afd241e7SCarlo Caione 25*afd241e7SCarlo CaioneBL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 26*afd241e7SCarlo Caione plat/common/plat_psci_common.c \ 27*afd241e7SCarlo Caione drivers/amlogic/console/aarch64/meson_console.S \ 28*afd241e7SCarlo Caione ${AML_PLAT_SOC}/${PLAT}_bl31_setup.c \ 29*afd241e7SCarlo Caione ${AML_PLAT_SOC}/${PLAT}_pm.c \ 30*afd241e7SCarlo Caione ${AML_PLAT_SOC}/${PLAT}_common.c \ 31*afd241e7SCarlo Caione ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \ 32*afd241e7SCarlo Caione ${AML_PLAT_COMMON}/aml_efuse.c \ 33*afd241e7SCarlo Caione ${AML_PLAT_COMMON}/aml_mhu.c \ 34*afd241e7SCarlo Caione ${AML_PLAT_COMMON}/aml_scpi.c \ 35*afd241e7SCarlo Caione ${AML_PLAT_COMMON}/aml_sip_svc.c \ 36*afd241e7SCarlo Caione ${AML_PLAT_COMMON}/aml_thermal.c \ 37*afd241e7SCarlo Caione ${AML_PLAT_COMMON}/aml_topology.c \ 38*afd241e7SCarlo Caione ${AML_PLAT_COMMON}/aml_console.c \ 39*afd241e7SCarlo Caione drivers/amlogic/crypto/sha_dma.c \ 40*afd241e7SCarlo Caione ${XLAT_TABLES_LIB_SRCS} \ 41*afd241e7SCarlo Caione ${GIC_SOURCES} 42*afd241e7SCarlo Caione 43*afd241e7SCarlo Caione# Tune compiler for Cortex-A53 44*afd241e7SCarlo Caioneifeq ($(notdir $(CC)),armclang) 45*afd241e7SCarlo Caione TF_CFLAGS_aarch64 += -mcpu=cortex-a53 46*afd241e7SCarlo Caioneelse ifneq ($(findstring clang,$(notdir $(CC))),) 47*afd241e7SCarlo Caione TF_CFLAGS_aarch64 += -mcpu=cortex-a53 48*afd241e7SCarlo Caioneelse 49*afd241e7SCarlo Caione TF_CFLAGS_aarch64 += -mtune=cortex-a53 50*afd241e7SCarlo Caioneendif 51*afd241e7SCarlo Caione 52*afd241e7SCarlo Caione# Build config flags 53*afd241e7SCarlo Caione# ------------------ 54*afd241e7SCarlo Caione 55*afd241e7SCarlo Caione# Enable all errata workarounds for Cortex-A53 56*afd241e7SCarlo CaioneERRATA_A53_855873 := 1 57*afd241e7SCarlo CaioneERRATA_A53_819472 := 1 58*afd241e7SCarlo CaioneERRATA_A53_824069 := 1 59*afd241e7SCarlo CaioneERRATA_A53_827319 := 1 60*afd241e7SCarlo Caione 61*afd241e7SCarlo CaioneWORKAROUND_CVE_2017_5715 := 0 62*afd241e7SCarlo Caione 63*afd241e7SCarlo Caione# Have different sections for code and rodata 64*afd241e7SCarlo CaioneSEPARATE_CODE_AND_RODATA := 1 65*afd241e7SCarlo Caione 66*afd241e7SCarlo Caione# Use Coherent memory 67*afd241e7SCarlo CaioneUSE_COHERENT_MEM := 1 68*afd241e7SCarlo Caione 69*afd241e7SCarlo Caione# Verify build config 70*afd241e7SCarlo Caione# ------------------- 71*afd241e7SCarlo Caione 72*afd241e7SCarlo Caioneifneq (${RESET_TO_BL31}, 0) 73*afd241e7SCarlo Caione $(error Error: ${PLAT} needs RESET_TO_BL31=0) 74*afd241e7SCarlo Caioneendif 75*afd241e7SCarlo Caione 76*afd241e7SCarlo Caioneifeq (${ARCH},aarch32) 77*afd241e7SCarlo Caione $(error Error: AArch32 not supported on ${PLAT}) 78*afd241e7SCarlo Caioneendif 79*afd241e7SCarlo Caione 80*afd241e7SCarlo Caioneall: ${BUILD_PLAT}/bl31.img 81*afd241e7SCarlo Caionedistclean realclean clean: cleanimage 82*afd241e7SCarlo Caione 83*afd241e7SCarlo Caionecleanimage: 84*afd241e7SCarlo Caione ${Q}${MAKE} -C ${DOIMAGEPATH} clean 85*afd241e7SCarlo Caione 86*afd241e7SCarlo Caione${DOIMAGETOOL}: 87*afd241e7SCarlo Caione ${Q}${MAKE} -C ${DOIMAGEPATH} 88*afd241e7SCarlo Caione 89*afd241e7SCarlo Caione${BUILD_PLAT}/bl31.img: ${BUILD_PLAT}/bl31.bin ${DOIMAGETOOL} 90*afd241e7SCarlo Caione ${DOIMAGETOOL} ${BUILD_PLAT}/bl31.bin ${BUILD_PLAT}/bl31.img 91*afd241e7SCarlo Caione 92