1*afd241e7SCarlo Caione /* 2*afd241e7SCarlo Caione * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3*afd241e7SCarlo Caione * 4*afd241e7SCarlo Caione * SPDX-License-Identifier: BSD-3-Clause 5*afd241e7SCarlo Caione */ 6*afd241e7SCarlo Caione 7*afd241e7SCarlo Caione #ifndef PLATFORM_DEF_H 8*afd241e7SCarlo Caione #define PLATFORM_DEF_H 9*afd241e7SCarlo Caione 10*afd241e7SCarlo Caione #include <arch.h> 11*afd241e7SCarlo Caione #include <lib/utils_def.h> 12*afd241e7SCarlo Caione 13*afd241e7SCarlo Caione #include "../axg_def.h" 14*afd241e7SCarlo Caione 15*afd241e7SCarlo Caione #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 16*afd241e7SCarlo Caione #define PLATFORM_LINKER_ARCH aarch64 17*afd241e7SCarlo Caione 18*afd241e7SCarlo Caione #define PLATFORM_STACK_SIZE UL(0x1000) 19*afd241e7SCarlo Caione 20*afd241e7SCarlo Caione #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 21*afd241e7SCarlo Caione #define PLATFORM_CLUSTER_COUNT U(1) 22*afd241e7SCarlo Caione #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 23*afd241e7SCarlo Caione #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT 24*afd241e7SCarlo Caione 25*afd241e7SCarlo Caione #define AML_PRIMARY_CPU U(0) 26*afd241e7SCarlo Caione 27*afd241e7SCarlo Caione #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 28*afd241e7SCarlo Caione #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 29*afd241e7SCarlo Caione PLATFORM_CORE_COUNT) 30*afd241e7SCarlo Caione 31*afd241e7SCarlo Caione #define PLAT_MAX_RET_STATE U(1) 32*afd241e7SCarlo Caione #define PLAT_MAX_OFF_STATE U(2) 33*afd241e7SCarlo Caione 34*afd241e7SCarlo Caione #define PLAT_SYS_CPU_CFG7 (U(1) << 25) 35*afd241e7SCarlo Caione #define PLAT_AO_TIMESTAMP_CNTL U(0x1ff) 36*afd241e7SCarlo Caione 37*afd241e7SCarlo Caione /* Local power state for power domains in Run state. */ 38*afd241e7SCarlo Caione #define PLAT_LOCAL_STATE_RUN U(0) 39*afd241e7SCarlo Caione /* Local power state for retention. Valid only for CPU power domains */ 40*afd241e7SCarlo Caione #define PLAT_LOCAL_STATE_RET U(1) 41*afd241e7SCarlo Caione /* Local power state for power-down. Valid for CPU and cluster power domains. */ 42*afd241e7SCarlo Caione #define PLAT_LOCAL_STATE_OFF U(2) 43*afd241e7SCarlo Caione 44*afd241e7SCarlo Caione /* 45*afd241e7SCarlo Caione * Macros used to parse state information from State-ID if it is using the 46*afd241e7SCarlo Caione * recommended encoding for State-ID. 47*afd241e7SCarlo Caione */ 48*afd241e7SCarlo Caione #define PLAT_LOCAL_PSTATE_WIDTH U(4) 49*afd241e7SCarlo Caione #define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1) 50*afd241e7SCarlo Caione 51*afd241e7SCarlo Caione /* 52*afd241e7SCarlo Caione * Some data must be aligned on the biggest cache line size in the platform. 53*afd241e7SCarlo Caione * This is known only to the platform as it might have a combination of 54*afd241e7SCarlo Caione * integrated and external caches. 55*afd241e7SCarlo Caione */ 56*afd241e7SCarlo Caione #define CACHE_WRITEBACK_SHIFT U(6) 57*afd241e7SCarlo Caione #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 58*afd241e7SCarlo Caione 59*afd241e7SCarlo Caione /* Memory-related defines */ 60*afd241e7SCarlo Caione #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 61*afd241e7SCarlo Caione #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 62*afd241e7SCarlo Caione 63*afd241e7SCarlo Caione #define MAX_MMAP_REGIONS 16 64*afd241e7SCarlo Caione #define MAX_XLAT_TABLES 8 65*afd241e7SCarlo Caione 66*afd241e7SCarlo Caione #endif /* PLATFORM_DEF_H */ 67