1 /* 2 * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <inttypes.h> 10 11 #include <drivers/scmi-msg.h> 12 #include <drivers/scmi.h> 13 #include <lib/mmio.h> 14 #include <lib/utils_def.h> 15 #include <platform_def.h> 16 #include <scmi.h> 17 18 #include "plat_private.h" 19 20 #define HIGH (1) 21 #define LOW (0) 22 23 struct scmi_clk { 24 unsigned long clock_id; 25 unsigned long rate; 26 const char *name; 27 bool enabled; 28 }; 29 30 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled, _rate) \ 31 [_scmi_id] = { \ 32 .clock_id = (_id), \ 33 .name = (_name), \ 34 .enabled = (_init_enabled), \ 35 .rate = (_rate), \ 36 } 37 38 static struct scmi_clk scmi0_clock[] = { 39 CLOCK_CELL(CLK_GEM0_0, CLK_GEM0_0, "gem0_pclk", true, 100000000), 40 CLOCK_CELL(CLK_GEM0_1, CLK_GEM0_1, "gem0_hclk", true, 100000000), 41 CLOCK_CELL(CLK_GEM0_2, CLK_GEM0_2, "gem0_tx_clk", true, 125000000), 42 CLOCK_CELL(CLK_GEM0_3, CLK_GEM0_3, "gem0_rx_clk", true, 100000000), 43 CLOCK_CELL(CLK_GEM0_4, CLK_GEM0_4, "gem0_tsu_clk", true, 100000000), 44 CLOCK_CELL(CLK_GEM1_0, CLK_GEM1_0, "gem1_pclk", true, 100000000), 45 CLOCK_CELL(CLK_GEM1_1, CLK_GEM1_1, "gem1_hclk", true, 100000000), 46 CLOCK_CELL(CLK_GEM1_2, CLK_GEM1_2, "gem1_tx_clk", true, 125000000), 47 CLOCK_CELL(CLK_GEM1_3, CLK_GEM1_3, "gem1_rx_clk", true, 100000000), 48 CLOCK_CELL(CLK_GEM1_4, CLK_GEM1_4, "gem1_tsu_clk", true, 100000000), 49 CLOCK_CELL(CLK_SERIAL0_0, CLK_SERIAL0_0, "uart0_uartclk", true, 100000000), 50 CLOCK_CELL(CLK_SERIAL0_1, CLK_SERIAL0_1, "uart0_apb_pclk", true, 100000000), 51 CLOCK_CELL(CLK_SERIAL1_0, CLK_SERIAL1_0, "uart1_uartclk", true, 100000000), 52 CLOCK_CELL(CLK_SERIAL1_1, CLK_SERIAL1_1, "uart1_apb_pclk", true, 100000000), 53 CLOCK_CELL(CLK_UFS0_0, CLK_UFS0_0, "ufs_core_clk", true, 100000000), 54 CLOCK_CELL(CLK_UFS0_1, CLK_UFS0_1, "ufs_phy_clk", true, 26000000), 55 CLOCK_CELL(CLK_UFS0_2, CLK_UFS0_2, "ufs_ref_pclk", true, 26000000), 56 CLOCK_CELL(CLK_USB0_0, CLK_USB0_0, "usb0_bus_clk", true, 100000000), 57 CLOCK_CELL(CLK_USB0_1, CLK_USB0_1, "usb0_ref_clk", true, 100000000), 58 CLOCK_CELL(CLK_USB0_2, CLK_USB0_2, "usb0_dwc_clk", true, 100000000), 59 CLOCK_CELL(CLK_USB1_0, CLK_USB1_0, "usb1_bus_clk", true, 100000000), 60 CLOCK_CELL(CLK_USB1_1, CLK_USB1_1, "usb1_ref_clk", true, 100000000), 61 CLOCK_CELL(CLK_USB1_2, CLK_USB1_2, "usb1_dwc_clk", true, 100000000), 62 CLOCK_CELL(CLK_MMC0_0, CLK_MMC0_0, "mmc0_xin_clk", true, 100000000), 63 CLOCK_CELL(CLK_MMC0_1, CLK_MMC0_1, "mmc0_ahb_clk", true, 100000000), 64 CLOCK_CELL(CLK_MMC0_2, CLK_MMC0_2, "mmc0_gate_clk", true, 100000000), 65 CLOCK_CELL(CLK_MMC1_0, CLK_MMC1_0, "mmc1_xin_clk", true, 100000000), 66 CLOCK_CELL(CLK_MMC1_1, CLK_MMC1_1, "mmc1_ahb_clk", true, 100000000), 67 CLOCK_CELL(CLK_MMC1_2, CLK_MMC1_2, "mmc1_gate_clk", true, 100000000), 68 CLOCK_CELL(CLK_TTC0_0, CLK_TTC0_0, "ttc0_clk", true, 100000000), 69 CLOCK_CELL(CLK_TTC1_0, CLK_TTC1_0, "ttc1_clk", true, 100000000), 70 CLOCK_CELL(CLK_TTC2_0, CLK_TTC2_0, "ttc2_clk", true, 100000000), 71 CLOCK_CELL(CLK_TTC3_0, CLK_TTC3_0, "ttc3_clk", true, 100000000), 72 CLOCK_CELL(CLK_TTC4_0, CLK_TTC4_0, "ttc4_clk", true, 100000000), 73 CLOCK_CELL(CLK_TTC5_0, CLK_TTC5_0, "ttc5_clk", true, 100000000), 74 CLOCK_CELL(CLK_TTC6_0, CLK_TTC6_0, "ttc6_clk", true, 100000000), 75 CLOCK_CELL(CLK_TTC7_0, CLK_TTC7_0, "ttc7_clk", true, 100000000), 76 CLOCK_CELL(CLK_I2C0_0, CLK_I2C0_0, "i2c0_clk", true, 100000000), 77 CLOCK_CELL(CLK_I2C1_0, CLK_I2C1_0, "i2c1_clk", true, 100000000), 78 CLOCK_CELL(CLK_I2C2_0, CLK_I2C2_0, "i2c2_clk", true, 100000000), 79 CLOCK_CELL(CLK_I2C3_0, CLK_I2C3_0, "i2c3_clk", true, 100000000), 80 CLOCK_CELL(CLK_I2C4_0, CLK_I2C4_0, "i2c4_clk", true, 100000000), 81 CLOCK_CELL(CLK_I2C5_0, CLK_I2C5_0, "i2c5_clk", true, 100000000), 82 CLOCK_CELL(CLK_I2C6_0, CLK_I2C6_0, "i2c6_clk", true, 100000000), 83 CLOCK_CELL(CLK_I2C7_0, CLK_I2C7_0, "i2c7_clk", true, 100000000), 84 CLOCK_CELL(CLK_OSPI0_0, CLK_OSPI0_0, "ospi0_clk", true, 100000000), 85 CLOCK_CELL(CLK_QSPI0_0, CLK_QSPI0_0, "qpsi0_ref_clk", true, 100000000), 86 CLOCK_CELL(CLK_QSPI0_1, CLK_QSPI0_1, "qspi0_pclk", true, 100000000), 87 CLOCK_CELL(CLK_WWDT0_0, CLK_WWDT0_0, "wwdt0_clk", true, 100000000), 88 CLOCK_CELL(CLK_WWDT1_0, CLK_WWDT1_0, "wwdt1_clk", true, 100000000), 89 CLOCK_CELL(CLK_WWDT2_0, CLK_WWDT2_0, "wwdt2_clk", true, 100000000), 90 CLOCK_CELL(CLK_WWDT3_0, CLK_WWDT3_0, "wwdt3_clk", true, 100000000), 91 CLOCK_CELL(CLK_ADMA0_0, CLK_ADMA0_0, "adma0_main_clk", true, 100000000), 92 CLOCK_CELL(CLK_ADMA0_1, CLK_ADMA0_1, "adma0_apb_clk", true, 100000000), 93 CLOCK_CELL(CLK_ADMA1_0, CLK_ADMA1_0, "adma1_main_clk", true, 100000000), 94 CLOCK_CELL(CLK_ADMA1_1, CLK_ADMA1_1, "adma1_apb_clk", true, 100000000), 95 CLOCK_CELL(CLK_ADMA2_0, CLK_ADMA2_0, "adma2_main_clk", true, 100000000), 96 CLOCK_CELL(CLK_ADMA2_1, CLK_ADMA2_1, "adma2_apb_clk", true, 100000000), 97 CLOCK_CELL(CLK_ADMA3_0, CLK_ADMA3_0, "adma3_main_clk", true, 100000000), 98 CLOCK_CELL(CLK_ADMA3_1, CLK_ADMA3_1, "adma3_apb_clk", true, 100000000), 99 CLOCK_CELL(CLK_ADMA4_0, CLK_ADMA4_0, "adma4_main_clk", true, 100000000), 100 CLOCK_CELL(CLK_ADMA4_1, CLK_ADMA4_1, "adma4_apb_clk", true, 100000000), 101 CLOCK_CELL(CLK_ADMA5_0, CLK_ADMA5_0, "adma5_main_clk", true, 100000000), 102 CLOCK_CELL(CLK_ADMA5_1, CLK_ADMA5_1, "adma5_apb_clk", true, 100000000), 103 CLOCK_CELL(CLK_ADMA6_0, CLK_ADMA6_0, "adma6_main_clk", true, 100000000), 104 CLOCK_CELL(CLK_ADMA6_1, CLK_ADMA6_1, "adma6_apb_clk", true, 100000000), 105 CLOCK_CELL(CLK_ADMA7_0, CLK_ADMA7_0, "adma7_main_clk", true, 100000000), 106 CLOCK_CELL(CLK_ADMA7_1, CLK_ADMA7_1, "adma7_apb_clk", true, 100000000), 107 CLOCK_CELL(CLK_CAN0_0, CLK_CAN0_0, "can0_can_clk", true, 100000000), 108 CLOCK_CELL(CLK_CAN0_1, CLK_CAN0_1, "can0_axi_clk", true, 100000000), 109 CLOCK_CELL(CLK_CAN1_0, CLK_CAN1_0, "can1_can_clk", true, 100000000), 110 CLOCK_CELL(CLK_CAN1_1, CLK_CAN1_1, "can1_axi_clk", true, 100000000), 111 CLOCK_CELL(CLK_CAN2_0, CLK_CAN2_0, "can2_can_clk", true, 100000000), 112 CLOCK_CELL(CLK_CAN2_1, CLK_CAN2_1, "can2_axi_clk", true, 100000000), 113 CLOCK_CELL(CLK_CAN3_0, CLK_CAN3_0, "can3_can_clk", true, 100000000), 114 CLOCK_CELL(CLK_CAN3_1, CLK_CAN3_1, "can3_axi_clk", true, 100000000), 115 CLOCK_CELL(CLK_PS_GPIO_0, CLK_PS_GPIO_0, "ps_gpio_clk", true, 100000000), 116 CLOCK_CELL(CLK_PMC_GPIO_0, CLK_PMC_GPIO_0, "pmc_gpio_clk", true, 100000000), 117 CLOCK_CELL(CLK_SPI0_0, CLK_SPI0_0, "spi0_ref_clk", true, 100000000), 118 CLOCK_CELL(CLK_SPI0_1, CLK_SPI0_1, "spi0_pclk", true, 100000000), 119 CLOCK_CELL(CLK_SPI1_0, CLK_SPI1_0, "spi1_ref_clk", true, 100000000), 120 CLOCK_CELL(CLK_SPI1_1, CLK_SPI1_1, "spi1_pclk", true, 100000000), 121 CLOCK_CELL(CLK_I3C0_0, CLK_I3C0_0, "i3c0_clk", true, 100000000), 122 CLOCK_CELL(CLK_I3C1_0, CLK_I3C1_0, "i3c1_clk", true, 100000000), 123 CLOCK_CELL(CLK_I3C2_0, CLK_I3C2_0, "i3c2_clk", true, 100000000), 124 CLOCK_CELL(CLK_I3C3_0, CLK_I3C3_0, "i3c3_clk", true, 100000000), 125 CLOCK_CELL(CLK_I3C4_0, CLK_I3C4_0, "i3c4_clk", true, 100000000), 126 CLOCK_CELL(CLK_I3C5_0, CLK_I3C5_0, "i3c5_clk", true, 100000000), 127 CLOCK_CELL(CLK_I3C6_0, CLK_I3C6_0, "i3c6_clk", true, 100000000), 128 CLOCK_CELL(CLK_I3C7_0, CLK_I3C7_0, "i3c7_clk", true, 100000000), 129 }; 130 131 /* 132 * struct scmi_reset - Data for the exposed reset controller 133 * @reset_id: Reset identifier in RCC reset driver 134 * @name: Reset string ID exposed to agent 135 */ 136 struct scmi_reset { 137 unsigned long reset_id; 138 const char *name; 139 }; 140 141 #define RESET_CELL(_scmi_id, _id, _name) \ 142 [_scmi_id] = { \ 143 .reset_id = (_id), \ 144 .name = (_name), \ 145 } 146 147 static struct scmi_reset scmi0_reset[] = { 148 RESET_CELL(RESET_GEM0_0, RESET_GEM0_0, "gem0"), 149 RESET_CELL(RESET_GEM1_0, RESET_GEM1_0, "gem1"), 150 RESET_CELL(RESET_SERIAL0_0, RESET_SERIAL0_0, "serial0"), 151 RESET_CELL(RESET_SERIAL1_0, RESET_SERIAL1_0, "serial1"), 152 RESET_CELL(RESET_UFS0_0, RESET_UFS0_0, "ufs0"), 153 RESET_CELL(RESET_I2C0_0, RESET_I2C0_0, "i2c0"), 154 RESET_CELL(RESET_I2C1_0, RESET_I2C1_0, "i2c1"), 155 RESET_CELL(RESET_I2C2_0, RESET_I2C2_0, "i2c2"), 156 RESET_CELL(RESET_I2C3_0, RESET_I2C3_0, "i2c3"), 157 RESET_CELL(RESET_I2C4_0, RESET_I2C4_0, "i2c4"), 158 RESET_CELL(RESET_I2C5_0, RESET_I2C5_0, "i2c5"), 159 RESET_CELL(RESET_I2C6_0, RESET_I2C6_0, "i2c6"), 160 RESET_CELL(RESET_I2C7_0, RESET_I2C7_0, "i2c7"), 161 RESET_CELL(RESET_I2C8_0, RESET_I2C8_0, "i2c8"), 162 RESET_CELL(RESET_OSPI0_0, RESET_OSPI0_0, "ospi"), 163 RESET_CELL(RESET_USB0_0, RESET_USB0_0, "usb0_0"), 164 RESET_CELL(RESET_USB0_1, RESET_USB0_1, "usb0_1"), 165 RESET_CELL(RESET_USB0_2, RESET_USB0_2, "usb0_2"), 166 RESET_CELL(RESET_USB1_0, RESET_USB1_0, "usb1_0"), 167 RESET_CELL(RESET_USB1_1, RESET_USB1_1, "usb1_1"), 168 RESET_CELL(RESET_USB1_2, RESET_USB1_2, "usb1_2"), 169 RESET_CELL(RESET_MMC0_0, RESET_MMC0_0, "mmc0"), 170 RESET_CELL(RESET_MMC1_0, RESET_MMC1_0, "mmc1"), 171 RESET_CELL(RESET_SPI0_0, RESET_SPI0_0, "spi0"), 172 RESET_CELL(RESET_SPI1_0, RESET_SPI1_0, "spi1"), 173 RESET_CELL(RESET_QSPI0_0, RESET_QSPI0_0, "qspi"), 174 RESET_CELL(RESET_I3C0_0, RESET_I3C0_0, "i3c0"), 175 RESET_CELL(RESET_I3C1_0, RESET_I3C1_0, "i3c1"), 176 RESET_CELL(RESET_I3C2_0, RESET_I3C2_0, "i3c2"), 177 RESET_CELL(RESET_I3C3_0, RESET_I3C3_0, "i3c3"), 178 RESET_CELL(RESET_I3C4_0, RESET_I3C4_0, "i3c4"), 179 RESET_CELL(RESET_I3C5_0, RESET_I3C5_0, "i3c5"), 180 RESET_CELL(RESET_I3C6_0, RESET_I3C6_0, "i3c6"), 181 RESET_CELL(RESET_I3C7_0, RESET_I3C7_0, "i3c7"), 182 RESET_CELL(RESET_I3C8_0, RESET_I3C8_0, "i3c8"), 183 RESET_CELL(RESET_UFSPHY_0, RESET_UFSPHY_0, "ufsphy0"), 184 }; 185 186 /** 187 * struct scmi_pd - Data for the exposed power domain controller 188 * @pd_id: pd identifier in RCC reset driver 189 * @name: pd string ID exposed to agent 190 * @state: keep state setting 191 */ 192 struct scmi_pd { 193 unsigned long pd_id; 194 const char *name; 195 unsigned int state; 196 }; 197 198 #define PD_CELL(_scmi_id, _id, _name, _state) \ 199 [_scmi_id] = { \ 200 .pd_id = _id, \ 201 .name = _name, \ 202 .state = _state, \ 203 } 204 205 static struct scmi_pd scmi0_pd[] = { 206 PD_CELL(PD_USB0, PD_USB0, "usb0", 0), 207 PD_CELL(PD_USB1, PD_USB1, "usb1", 0), 208 }; 209 210 struct scmi_resources { 211 struct scmi_clk *clock; 212 size_t clock_count; 213 struct scmi_reset *reset; 214 size_t reset_count; 215 struct scmi_pd *pd; 216 size_t pd_count; 217 }; 218 219 static const struct scmi_resources resources[] = { 220 [0] = { 221 .clock = scmi0_clock, 222 .clock_count = ARRAY_SIZE(scmi0_clock), 223 .reset = scmi0_reset, 224 .reset_count = ARRAY_SIZE(scmi0_reset), 225 .pd = scmi0_pd, 226 .pd_count = ARRAY_SIZE(scmi0_pd), 227 }, 228 }; 229 230 static const struct scmi_resources *find_resource(unsigned int agent_id) 231 { 232 assert(agent_id < ARRAY_SIZE(resources)); 233 234 return &resources[agent_id]; 235 } 236 237 static struct scmi_clk *clk_find(unsigned int agent_id, unsigned int scmi_id) 238 { 239 const struct scmi_resources *resource = find_resource(agent_id); 240 size_t n = 0U; 241 struct scmi_clk *ret = NULL; 242 243 if (resource != NULL) { 244 for (n = 0U; n < resource->clock_count; n++) { 245 if (n == scmi_id) { 246 ret = &resource->clock[n]; 247 break; 248 } 249 } 250 } 251 252 return ret; 253 } 254 255 size_t plat_scmi_clock_count(unsigned int agent_id) 256 { 257 const struct scmi_resources *resource = find_resource(agent_id); 258 size_t ret; 259 260 if (resource == NULL) { 261 ret = 0U; 262 } else { 263 VERBOSE("SCMI: CLK: %d clocks\n", (unsigned int)resource->clock_count); 264 265 ret = resource->clock_count; 266 } 267 return ret; 268 } 269 270 const char *plat_scmi_clock_get_name(unsigned int agent_id, unsigned int scmi_id) 271 { 272 const struct scmi_clk *clock = clk_find(agent_id, scmi_id); 273 const char *ret; 274 275 if (clock == NULL) { 276 ret = NULL; 277 } else { 278 VERBOSE("SCMI: CLK: id: %d, get_name: %s\n", scmi_id, clock->name); 279 280 ret = clock->name; 281 } 282 return ret; 283 }; 284 285 /* Called by Linux */ 286 int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id, 287 unsigned long *array, size_t *nb_elts, 288 uint32_t start_idx) 289 { 290 const struct scmi_clk *clock = clk_find(agent_id, scmi_id); 291 int32_t ret = SCMI_SUCCESS; 292 293 if (clock == NULL) { 294 ret = SCMI_NOT_FOUND; 295 goto exit_label; 296 } 297 298 if (start_idx > 0U) { 299 ret = SCMI_OUT_OF_RANGE; 300 goto exit_label; 301 } 302 303 if (array == NULL) { 304 *nb_elts = 1U; 305 } else if (*nb_elts == 1U) { 306 *array = clock->rate; 307 VERBOSE("SCMI: CLK: id: %d, clk_name: %s, get_rate %lu\n", 308 scmi_id, clock->name, *array); 309 } else { 310 ret = SCMI_GENERIC_ERROR; 311 } 312 313 exit_label: 314 return ret; 315 } 316 317 unsigned long plat_scmi_clock_get_rate(unsigned int agent_id, unsigned int scmi_id) 318 { 319 const struct scmi_clk *clock = clk_find(agent_id, scmi_id); 320 unsigned long ret; 321 322 if (clock == NULL) { 323 ret = SCMI_NOT_FOUND; 324 } else { 325 VERBOSE("SCMI: CLK: id: %d, get_rate: %lu\n", scmi_id, clock->rate); 326 ret = clock->rate; 327 } 328 return ret; 329 } 330 331 int32_t plat_scmi_clock_set_rate(unsigned int agent_id, unsigned int scmi_id, 332 unsigned long rate) 333 { 334 struct scmi_clk *clock = clk_find(agent_id, scmi_id); 335 int32_t ret = SCMI_SUCCESS; 336 337 if (clock == NULL) { 338 ret = SCMI_NOT_FOUND; 339 } else { 340 VERBOSE("SCMI: CLK: id: %d, set_rate: %lu\n", scmi_id, rate); 341 clock->rate = rate; 342 } 343 return ret; 344 } 345 346 int32_t plat_scmi_clock_get_state(unsigned int agent_id, unsigned int scmi_id) 347 { 348 const struct scmi_clk *clock = clk_find(agent_id, scmi_id); 349 int32_t ret; 350 351 if (clock == NULL) { 352 ret = SCMI_NOT_FOUND; 353 } else { 354 VERBOSE("SCMI: CLK: id: %d, get_state: %d\n", scmi_id, clock->enabled); 355 356 if (clock->enabled) { 357 ret = HIGH; 358 } else { 359 ret = LOW; 360 } 361 } 362 return ret; 363 } 364 365 int32_t plat_scmi_clock_set_state(unsigned int agent_id, unsigned int scmi_id, 366 bool enable_not_disable) 367 { 368 struct scmi_clk *clock = clk_find(agent_id, scmi_id); 369 int32_t ret; 370 371 if (clock == NULL) { 372 ret = SCMI_NOT_FOUND; 373 } else { 374 if (enable_not_disable) { 375 if (!clock->enabled) { 376 VERBOSE("SCMI: clock: %u enable\n", scmi_id); 377 clock->enabled = true; 378 } 379 } else { 380 if (clock->enabled) { 381 VERBOSE("SCMI: clock: %u disable\n", scmi_id); 382 clock->enabled = false; 383 } 384 } 385 386 VERBOSE("SCMI: CLK: id: %d, set_state: %d\n", scmi_id, clock->enabled); 387 388 ret = SCMI_SUCCESS; 389 } 390 391 return ret; 392 } 393 394 395 /* 396 * Platform SCMI reset domains 397 */ 398 static struct scmi_reset *find_reset(unsigned int agent_id, 399 unsigned int scmi_id) 400 { 401 const struct scmi_resources *resource = find_resource(agent_id); 402 size_t n; 403 404 if (resource != NULL) { 405 for (n = 0U; n < resource->reset_count; n++) { 406 if (n == scmi_id) { 407 return &resource->reset[n]; 408 } 409 } 410 } 411 412 return NULL; 413 } 414 415 const char *plat_scmi_rstd_get_name(unsigned int agent_id, unsigned int scmi_id) 416 { 417 const struct scmi_reset *reset = find_reset(agent_id, scmi_id); 418 419 if (reset == NULL) { 420 return NULL; 421 } 422 423 return reset->name; 424 } 425 426 size_t plat_scmi_rstd_count(unsigned int agent_id) 427 { 428 const struct scmi_resources *resource = find_resource(agent_id); 429 430 if (resource == NULL) { 431 return 0U; 432 } 433 434 return resource->reset_count; 435 } 436 437 int32_t plat_scmi_rstd_autonomous(unsigned int agent_id, unsigned int scmi_id, 438 uint32_t state) 439 { 440 const struct scmi_reset *reset = find_reset(agent_id, scmi_id); 441 442 if (reset == NULL) { 443 return SCMI_NOT_FOUND; 444 } 445 446 /* Supports only reset with context loss */ 447 if (state != 0U) { 448 return SCMI_NOT_SUPPORTED; 449 } 450 451 NOTICE("SCMI reset on ID %lu/%s\n", 452 reset->reset_id, plat_scmi_rstd_get_name(agent_id, scmi_id)); 453 454 return SCMI_SUCCESS; 455 } 456 457 int32_t plat_scmi_rstd_set_state(unsigned int agent_id, unsigned int scmi_id, 458 bool assert_not_deassert) 459 { 460 const struct scmi_reset *reset = find_reset(agent_id, scmi_id); 461 462 if (reset == NULL) { 463 return SCMI_NOT_FOUND; 464 } 465 466 if (assert_not_deassert) { 467 NOTICE("SCMI reset %lu/%s set\n", 468 reset->reset_id, plat_scmi_rstd_get_name(agent_id, scmi_id)); 469 470 switch (scmi_id) { 471 case RESET_UFS0_0: 472 mmio_write_32(PMXC_CRP_RST_UFS, 1); 473 break; 474 case RESET_UFSPHY_0: 475 mmio_write_32(PMXC_IOU_SLCR_PHY_RESET, 1); 476 break; 477 default: 478 break; 479 } 480 } else { 481 NOTICE("SCMI reset %lu/%s release\n", 482 reset->reset_id, plat_scmi_rstd_get_name(agent_id, scmi_id)); 483 484 switch (scmi_id) { 485 case RESET_UFS0_0: 486 mmio_write_32(PMXC_CRP_RST_UFS, 0); 487 break; 488 case RESET_UFSPHY_0: 489 mmio_write_32(PMXC_IOU_SLCR_PHY_RESET, 0); 490 break; 491 default: 492 break; 493 } 494 } 495 496 return SCMI_SUCCESS; 497 } 498 499 /* 500 * Platform SCMI reset domains 501 */ 502 static struct scmi_pd *find_pd(unsigned int agent_id, unsigned int pd_id) 503 { 504 const struct scmi_resources *resource = find_resource(agent_id); 505 size_t n; 506 507 if (resource != NULL) { 508 for (n = 0U; n < resource->pd_count; n++) { 509 if (n == pd_id) { 510 return &resource->pd[n]; 511 } 512 } 513 } 514 515 return NULL; 516 } 517 518 size_t plat_scmi_pd_count(unsigned int agent_id) 519 { 520 const struct scmi_resources *resource = find_resource(agent_id); 521 size_t ret; 522 523 if (resource == NULL) { 524 ret = 0U; 525 } else { 526 ret = resource->pd_count; 527 528 NOTICE("SCMI: PD: %d\n", (unsigned int)ret); 529 } 530 return ret; 531 } 532 533 const char *plat_scmi_pd_get_name(unsigned int agent_id, unsigned int pd_id) 534 { 535 const struct scmi_pd *pd = find_pd(agent_id, pd_id); 536 const char *ret = NULL; 537 538 if (pd != NULL) { 539 ret = pd->name; 540 } 541 542 return ret; 543 } 544 545 unsigned int plat_scmi_pd_statistics(unsigned int agent_id, unsigned long *pd_id) 546 { 547 return 0U; 548 } 549 550 unsigned int plat_scmi_pd_get_attributes(unsigned int agent_id, unsigned int pd_id) 551 { 552 return 0U; 553 } 554 555 unsigned int plat_scmi_pd_get_state(unsigned int agent_id, unsigned int pd_id) 556 { 557 const struct scmi_pd *pd = find_pd(agent_id, pd_id); 558 uint32_t ret = SCMI_NOT_SUPPORTED; 559 560 if (pd != NULL) { 561 NOTICE("SCMI: PD: get id: %d, state: %x\n", pd_id, pd->state); 562 563 ret = pd->state; 564 } 565 566 return ret; 567 } 568 569 int32_t plat_scmi_pd_set_state(unsigned int agent_id, unsigned int flags, unsigned int pd_id, 570 unsigned int state) 571 { 572 struct scmi_pd *pd = find_pd(agent_id, pd_id); 573 int32_t ret = SCMI_SUCCESS; 574 575 if (pd == NULL) { 576 ret = SCMI_NOT_SUPPORTED; 577 goto exit_label; 578 } 579 580 NOTICE("SCMI: PD: set id: %d, orig state: %x, new state: %x, flags: %x\n", 581 pd_id, pd->state, state, flags); 582 583 pd->state = state; 584 585 exit_label: 586 return ret; 587 } 588 589 590 /* Currently only one channel is supported. Expectation is that channel 0 is used by NS SW */ 591 static struct scmi_msg_channel scmi_channel[] = { 592 [0] = { 593 .shm_addr = SMT_BUFFER_BASE, 594 .shm_size = SMT_BUF_SLOT_SIZE, 595 }, 596 }; 597 598 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int agent_id) 599 { 600 assert(agent_id < ARRAY_SIZE(scmi_channel)); 601 602 VERBOSE("%d: SCMI asking for channel\n", agent_id); 603 604 /* Just in case that code is reused */ 605 return &scmi_channel[agent_id]; 606 } 607 608 /* Base protocol implementations */ 609 const char *plat_scmi_vendor_name(void) 610 { 611 return SCMI_VENDOR; 612 } 613 614 const char *plat_scmi_sub_vendor_name(void) 615 { 616 return SCMI_PRODUCT; 617 } 618 619 /* Currently supporting Clocks and Reset Domains */ 620 static const uint8_t plat_protocol_list[] = { 621 SCMI_PROTOCOL_ID_BASE, 622 SCMI_PROTOCOL_ID_CLOCK, 623 SCMI_PROTOCOL_ID_RESET_DOMAIN, 624 SCMI_PROTOCOL_ID_POWER_DOMAIN, 625 /* SCMI_PROTOCOL_ID_SENSOR, */ 626 0U /* Null termination */ 627 }; 628 629 size_t plat_scmi_protocol_count(void) 630 { 631 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1U; 632 633 VERBOSE("SCMI: Protocol count: %d\n", (int32_t)count); 634 635 return count; 636 } 637 638 const uint8_t *plat_scmi_protocol_list(unsigned int agent_id __unused) 639 { 640 return plat_protocol_list; 641 } 642 643 void init_scmi_server(void) 644 { 645 size_t i; 646 int32_t ret; 647 648 for (i = 0U; i < ARRAY_SIZE(scmi_channel); i++) { 649 scmi_smt_init_agent_channel(&scmi_channel[i]); 650 } 651 652 INFO("SCMI: Server initialized\n"); 653 654 if (platform_id == QEMU) { 655 /* default setting is for QEMU */ 656 } else if (platform_id == SPP) { 657 for (i = 0U; i < ARRAY_SIZE(scmi0_clock); i++) { 658 659 /* Keep i2c on 100MHz to calculate rates properly */ 660 if ((i >= CLK_I2C0_0) && (i <= CLK_I2C7_0)) { 661 continue; 662 } 663 664 /* Keep UFS clocks to default values to get the expected rates */ 665 if ((i >= CLK_UFS0_0) && (i <= CLK_UFS0_2)) { 666 continue; 667 } 668 669 /* 670 * SPP supports multiple versions. 671 * The cpu_clock value is set to corresponding SPP 672 * version in early platform setup, resuse the same 673 * value here. 674 */ 675 ret = plat_scmi_clock_set_rate(0, i, cpu_clock); 676 if (ret < 0) { 677 NOTICE("Failed to set clock rate for SPP scmi_id=%ld\n", i); 678 } 679 } 680 } else { 681 /* Making MISRA C 2012 15.7 compliant */ 682 } 683 } 684