1*c97857dbSAmit Nagal /* 2*c97857dbSAmit Nagal * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. 3*c97857dbSAmit Nagal * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4*c97857dbSAmit Nagal * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. 5*c97857dbSAmit Nagal * 6*c97857dbSAmit Nagal * SPDX-License-Identifier: BSD-3-Clause 7*c97857dbSAmit Nagal */ 8*c97857dbSAmit Nagal 9*c97857dbSAmit Nagal #include <common/debug.h> 10*c97857dbSAmit Nagal #include <plat/common/platform.h> 11*c97857dbSAmit Nagal #include <platform_def.h> 12*c97857dbSAmit Nagal 13*c97857dbSAmit Nagal #include <plat_private.h> 14*c97857dbSAmit Nagal 15*c97857dbSAmit Nagal static const uint8_t plat_power_domain_tree_desc[] = { 16*c97857dbSAmit Nagal /* Number of root nodes */ 17*c97857dbSAmit Nagal 1, 18*c97857dbSAmit Nagal /* Number of clusters */ 19*c97857dbSAmit Nagal PLATFORM_CLUSTER_COUNT, 20*c97857dbSAmit Nagal /* Number of children for the first cluster node */ 21*c97857dbSAmit Nagal PLATFORM_CORE_COUNT_PER_CLUSTER, 22*c97857dbSAmit Nagal /* Number of children for the second cluster node */ 23*c97857dbSAmit Nagal PLATFORM_CORE_COUNT_PER_CLUSTER, 24*c97857dbSAmit Nagal /* Number of children for the third cluster node */ 25*c97857dbSAmit Nagal PLATFORM_CORE_COUNT_PER_CLUSTER, 26*c97857dbSAmit Nagal /* Number of children for the fourth cluster node */ 27*c97857dbSAmit Nagal PLATFORM_CORE_COUNT_PER_CLUSTER, 28*c97857dbSAmit Nagal }; 29*c97857dbSAmit Nagal 30*c97857dbSAmit Nagal const uint8_t *plat_get_power_domain_tree_desc(void) 31*c97857dbSAmit Nagal { 32*c97857dbSAmit Nagal return plat_power_domain_tree_desc; 33*c97857dbSAmit Nagal } 34*c97857dbSAmit Nagal 35*c97857dbSAmit Nagal /******************************************************************************* 36*c97857dbSAmit Nagal * This function implements a part of the critical interface between the psci 37*c97857dbSAmit Nagal * generic layer and the platform that allows the former to query the platform 38*c97857dbSAmit Nagal * to convert an MPIDR to a unique linear index. An error code (-1) is returned 39*c97857dbSAmit Nagal * in case the MPIDR is invalid. 40*c97857dbSAmit Nagal ******************************************************************************/ 41*c97857dbSAmit Nagal int32_t plat_core_pos_by_mpidr(u_register_t mpidr) 42*c97857dbSAmit Nagal { 43*c97857dbSAmit Nagal uint32_t cluster_id, cpu_id; 44*c97857dbSAmit Nagal 45*c97857dbSAmit Nagal mpidr &= MPIDR_AFFINITY_MASK; 46*c97857dbSAmit Nagal 47*c97857dbSAmit Nagal cluster_id = MPIDR_AFFLVL2_VAL(mpidr); 48*c97857dbSAmit Nagal cpu_id = MPIDR_AFFLVL1_VAL(mpidr); 49*c97857dbSAmit Nagal 50*c97857dbSAmit Nagal if (cluster_id >= PLATFORM_CLUSTER_COUNT) { 51*c97857dbSAmit Nagal return -3; 52*c97857dbSAmit Nagal } 53*c97857dbSAmit Nagal 54*c97857dbSAmit Nagal /* 55*c97857dbSAmit Nagal * Validate cpu_id by checking whether it represents a CPU in 56*c97857dbSAmit Nagal * one of the two clusters present on the platform. 57*c97857dbSAmit Nagal */ 58*c97857dbSAmit Nagal if (cpu_id >= PLATFORM_CORE_COUNT_PER_CLUSTER) { 59*c97857dbSAmit Nagal return -1; 60*c97857dbSAmit Nagal } 61*c97857dbSAmit Nagal 62*c97857dbSAmit Nagal return (cpu_id + (cluster_id * PLATFORM_CORE_COUNT_PER_CLUSTER)); 63*c97857dbSAmit Nagal } 64