1*c3ab09d1SSaivardhan Thatikonda /* 2*c3ab09d1SSaivardhan Thatikonda * Copyright (c) 2025, Advanced Micro Devices, Inc. All rights reserved. 3*c3ab09d1SSaivardhan Thatikonda * 4*c3ab09d1SSaivardhan Thatikonda * SPDX-License-Identifier: BSD-3-Clause 5*c3ab09d1SSaivardhan Thatikonda */ 6*c3ab09d1SSaivardhan Thatikonda #include <common/debug.h> 7*c3ab09d1SSaivardhan Thatikonda #include <lib/mmio.h> 8*c3ab09d1SSaivardhan Thatikonda 9*c3ab09d1SSaivardhan Thatikonda #include <plat_ocm_coherency.h> 10*c3ab09d1SSaivardhan Thatikonda #include <platform_def.h> 11*c3ab09d1SSaivardhan Thatikonda 12*c3ab09d1SSaivardhan Thatikonda /* 13*c3ab09d1SSaivardhan Thatikonda * Register non hash mem regions addresses 14*c3ab09d1SSaivardhan Thatikonda */ 15*c3ab09d1SSaivardhan Thatikonda #define POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 U(0xF8168000) 16*c3ab09d1SSaivardhan Thatikonda #define NON_HASH_MEM_REGION_REG0 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC08) 17*c3ab09d1SSaivardhan Thatikonda #define NON_HASH_MEM_REGION_REG1 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC0C) 18*c3ab09d1SSaivardhan Thatikonda #define NON_HASH_MEM_REGION_REG2 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC10) 19*c3ab09d1SSaivardhan Thatikonda #define NON_HASH_MEM_REGION_REG3 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC14) 20*c3ab09d1SSaivardhan Thatikonda #define NON_HASH_MEM_REGION_REG4 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC18) 21*c3ab09d1SSaivardhan Thatikonda #define NON_HASH_MEM_REGION_REG5 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC1C) 22*c3ab09d1SSaivardhan Thatikonda #define NON_HASH_MEM_REGION_REG6 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC20) 23*c3ab09d1SSaivardhan Thatikonda #define NON_HASH_MEM_REGION_REG7 U(POR_RNSAM_NODE_INFO_U_RNFBESAM_NID12 + 0xC24) 24*c3ab09d1SSaivardhan Thatikonda 25*c3ab09d1SSaivardhan Thatikonda #define REGION_BASE_ADDR_VALUE U(0x2E) 26*c3ab09d1SSaivardhan Thatikonda #define REGION_BASE_ADDR_SHIFT 9 27*c3ab09d1SSaivardhan Thatikonda 28*c3ab09d1SSaivardhan Thatikonda #define REGION_BASE_ADDRESS_MASK GENMASK(30, REGION_BASE_ADDR_SHIFT) 29*c3ab09d1SSaivardhan Thatikonda #define REGION_VALID_BIT BIT(0) 30*c3ab09d1SSaivardhan Thatikonda 31*c3ab09d1SSaivardhan Thatikonda /* 32*c3ab09d1SSaivardhan Thatikonda * verify the register configured as non-hashed 33*c3ab09d1SSaivardhan Thatikonda */ 34*c3ab09d1SSaivardhan Thatikonda #define IS_NON_HASHED_REGION(reg) \ 35*c3ab09d1SSaivardhan Thatikonda ((FIELD_GET(REGION_BASE_ADDRESS_MASK, mmio_read_32(reg)) == REGION_BASE_ADDR_VALUE) && \ 36*c3ab09d1SSaivardhan Thatikonda (mmio_read_32(reg) & REGION_VALID_BIT)) 37*c3ab09d1SSaivardhan Thatikonda 38*c3ab09d1SSaivardhan Thatikonda /* 39*c3ab09d1SSaivardhan Thatikonda * Splitter registers 40*c3ab09d1SSaivardhan Thatikonda */ 41*c3ab09d1SSaivardhan Thatikonda #define FPX_SPLITTER_0 U(0xECC20000) 42*c3ab09d1SSaivardhan Thatikonda #define FPX_SPLITTER_1 U(0xECD20000) 43*c3ab09d1SSaivardhan Thatikonda #define FPX_SPLITTER_2 U(0xECE20000) 44*c3ab09d1SSaivardhan Thatikonda #define FPX_SPLITTER_3 U(0xECF20000) 45*c3ab09d1SSaivardhan Thatikonda #define OCM_ADDR_DIST_MODE BIT(16) 46*c3ab09d1SSaivardhan Thatikonda 47*c3ab09d1SSaivardhan Thatikonda #define OCM_COHERENT 0 48*c3ab09d1SSaivardhan Thatikonda #define OCM_NOT_COHERENT 1 49*c3ab09d1SSaivardhan Thatikonda #define TFA_NOT_IN_OCM 2 50*c3ab09d1SSaivardhan Thatikonda 51*c3ab09d1SSaivardhan Thatikonda /* 52*c3ab09d1SSaivardhan Thatikonda * Function that verifies the OCM is coherent or not with the following checks: 53*c3ab09d1SSaivardhan Thatikonda * verify that OCM is in non hashed region or not if not then verify 54*c3ab09d1SSaivardhan Thatikonda * OCM_ADDR_DIST_MODE bit in splitter registers is set. 55*c3ab09d1SSaivardhan Thatikonda */ check_ocm_coherency(void)56*c3ab09d1SSaivardhan Thatikondaint32_t check_ocm_coherency(void) 57*c3ab09d1SSaivardhan Thatikonda { 58*c3ab09d1SSaivardhan Thatikonda int32_t status = OCM_COHERENT; 59*c3ab09d1SSaivardhan Thatikonda /* isolation should be disabled in order to read these registers */ 60*c3ab09d1SSaivardhan Thatikonda if ((IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG0) || 61*c3ab09d1SSaivardhan Thatikonda IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG1) || 62*c3ab09d1SSaivardhan Thatikonda IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG2) || 63*c3ab09d1SSaivardhan Thatikonda IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG3) || 64*c3ab09d1SSaivardhan Thatikonda IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG4) || 65*c3ab09d1SSaivardhan Thatikonda IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG5) || 66*c3ab09d1SSaivardhan Thatikonda IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG6) || 67*c3ab09d1SSaivardhan Thatikonda IS_NON_HASHED_REGION(NON_HASH_MEM_REGION_REG7))) { 68*c3ab09d1SSaivardhan Thatikonda WARN("OCM is not configured as coherent\n"); 69*c3ab09d1SSaivardhan Thatikonda status = OCM_NOT_COHERENT; 70*c3ab09d1SSaivardhan Thatikonda } else { 71*c3ab09d1SSaivardhan Thatikonda /* verify OCM_ADDR_DIST_MODE bit in splitter registers is set */ 72*c3ab09d1SSaivardhan Thatikonda if (!((mmio_read_32(FPX_SPLITTER_0) & OCM_ADDR_DIST_MODE) && 73*c3ab09d1SSaivardhan Thatikonda (mmio_read_32(FPX_SPLITTER_1) & OCM_ADDR_DIST_MODE) && 74*c3ab09d1SSaivardhan Thatikonda (mmio_read_32(FPX_SPLITTER_2) & OCM_ADDR_DIST_MODE) && 75*c3ab09d1SSaivardhan Thatikonda (mmio_read_32(FPX_SPLITTER_3) & OCM_ADDR_DIST_MODE))) { 76*c3ab09d1SSaivardhan Thatikonda WARN("OCM is not configured as coherent\n"); 77*c3ab09d1SSaivardhan Thatikonda status = OCM_NOT_COHERENT; 78*c3ab09d1SSaivardhan Thatikonda } 79*c3ab09d1SSaivardhan Thatikonda } 80*c3ab09d1SSaivardhan Thatikonda return status; 81*c3ab09d1SSaivardhan Thatikonda } 82*c3ab09d1SSaivardhan Thatikonda 83