1*c97857dbSAmit Nagal /* 2*c97857dbSAmit Nagal * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3*c97857dbSAmit Nagal * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4*c97857dbSAmit Nagal * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5*c97857dbSAmit Nagal * 6*c97857dbSAmit Nagal * SPDX-License-Identifier: BSD-3-Clause 7*c97857dbSAmit Nagal */ 8*c97857dbSAmit Nagal 9*c97857dbSAmit Nagal #ifndef PLATFORM_DEF_H 10*c97857dbSAmit Nagal #define PLATFORM_DEF_H 11*c97857dbSAmit Nagal 12*c97857dbSAmit Nagal #include <arch.h> 13*c97857dbSAmit Nagal #include "def.h" 14*c97857dbSAmit Nagal 15*c97857dbSAmit Nagal /******************************************************************************* 16*c97857dbSAmit Nagal * Generic platform constants 17*c97857dbSAmit Nagal ******************************************************************************/ 18*c97857dbSAmit Nagal 19*c97857dbSAmit Nagal /* Size of cacheable stacks */ 20*c97857dbSAmit Nagal #define PLATFORM_STACK_SIZE U(0x440) 21*c97857dbSAmit Nagal 22*c97857dbSAmit Nagal #define PLATFORM_CLUSTER_COUNT U(4) 23*c97857dbSAmit Nagal #define PLATFORM_CORE_COUNT_PER_CLUSTER U(2) /* 2 CPUs per cluster */ 24*c97857dbSAmit Nagal 25*c97857dbSAmit Nagal #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * PLATFORM_CORE_COUNT_PER_CLUSTER) 26*c97857dbSAmit Nagal 27*c97857dbSAmit Nagal #define PLAT_MAX_PWR_LVL U(2) 28*c97857dbSAmit Nagal #define PLAT_MAX_RET_STATE U(1) 29*c97857dbSAmit Nagal #define PLAT_MAX_OFF_STATE U(2) 30*c97857dbSAmit Nagal 31*c97857dbSAmit Nagal /******************************************************************************* 32*c97857dbSAmit Nagal * BL31 specific defines. 33*c97857dbSAmit Nagal ******************************************************************************/ 34*c97857dbSAmit Nagal /* 35*c97857dbSAmit Nagal * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 36*c97857dbSAmit Nagal * present). BL31_BASE is calculated using the current BL31 debug size plus a 37*c97857dbSAmit Nagal * little space for growth. 38*c97857dbSAmit Nagal */ 39*c97857dbSAmit Nagal #ifndef MEM_BASE 40*c97857dbSAmit Nagal # define BL31_BASE U(0xBBF00000) 41*c97857dbSAmit Nagal # define BL31_LIMIT U(0xBC000000) 42*c97857dbSAmit Nagal #else 43*c97857dbSAmit Nagal # define BL31_BASE U(MEM_BASE) 44*c97857dbSAmit Nagal # define BL31_LIMIT U(MEM_BASE + MEM_SIZE) 45*c97857dbSAmit Nagal # ifdef MEM_PROGBITS_SIZE 46*c97857dbSAmit Nagal # define BL31_PROGBITS_LIMIT U(MEM_BASE + \ 47*c97857dbSAmit Nagal MEM_PROGBITS_SIZE) 48*c97857dbSAmit Nagal # endif 49*c97857dbSAmit Nagal #endif 50*c97857dbSAmit Nagal 51*c97857dbSAmit Nagal /******************************************************************************* 52*c97857dbSAmit Nagal * BL32 specific defines. 53*c97857dbSAmit Nagal ******************************************************************************/ 54*c97857dbSAmit Nagal #ifndef BL32_MEM_BASE 55*c97857dbSAmit Nagal # define BL32_BASE U(0x60000000) 56*c97857dbSAmit Nagal # define BL32_LIMIT U(0x80000000) 57*c97857dbSAmit Nagal #else 58*c97857dbSAmit Nagal # define BL32_BASE U(BL32_MEM_BASE) 59*c97857dbSAmit Nagal # define BL32_LIMIT U(BL32_MEM_BASE + BL32_MEM_SIZE) 60*c97857dbSAmit Nagal #endif 61*c97857dbSAmit Nagal 62*c97857dbSAmit Nagal /******************************************************************************* 63*c97857dbSAmit Nagal * BL33 specific defines. 64*c97857dbSAmit Nagal ******************************************************************************/ 65*c97857dbSAmit Nagal #ifndef PRELOADED_BL33_BASE 66*c97857dbSAmit Nagal # define PLAT_ARM_NS_IMAGE_BASE U(0x8000000) 67*c97857dbSAmit Nagal #else 68*c97857dbSAmit Nagal # define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) 69*c97857dbSAmit Nagal #endif 70*c97857dbSAmit Nagal 71*c97857dbSAmit Nagal /******************************************************************************* 72*c97857dbSAmit Nagal * TSP specific defines. 73*c97857dbSAmit Nagal ******************************************************************************/ 74*c97857dbSAmit Nagal #define TSP_SEC_MEM_BASE BL32_BASE 75*c97857dbSAmit Nagal #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE) 76*c97857dbSAmit Nagal 77*c97857dbSAmit Nagal /* ID of the secure physical generic timer interrupt used by the TSP */ 78*c97857dbSAmit Nagal #define ARM_IRQ_SEC_PHY_TIMER U(29) 79*c97857dbSAmit Nagal #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 80*c97857dbSAmit Nagal 81*c97857dbSAmit Nagal /******************************************************************************* 82*c97857dbSAmit Nagal * Platform specific page table and MMU setup constants 83*c97857dbSAmit Nagal ******************************************************************************/ 84*c97857dbSAmit Nagal #define PLAT_DDR_LOWMEM_MAX U(0x80000000) 85*c97857dbSAmit Nagal 86*c97857dbSAmit Nagal #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32U) 87*c97857dbSAmit Nagal #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32U) 88*c97857dbSAmit Nagal 89*c97857dbSAmit Nagal #define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) 90*c97857dbSAmit Nagal 91*c97857dbSAmit Nagal #define PLAT_OCM_BASE U(0xBBF00000) 92*c97857dbSAmit Nagal #define PLAT_OCM_LIMIT U(0xBC000000) 93*c97857dbSAmit Nagal 94*c97857dbSAmit Nagal #if defined(TRANSFER_LIST) 95*c97857dbSAmit Nagal /* 96*c97857dbSAmit Nagal * FIXME: This address should come from firmware before TF-A 97*c97857dbSAmit Nagal * Having this to make sure the transfer list functionality works 98*c97857dbSAmit Nagal */ 99*c97857dbSAmit Nagal #define FW_HANDOFF_BASE U(0x70000000) 100*c97857dbSAmit Nagal #define FW_HANDOFF_SIZE U(0x10000) 101*c97857dbSAmit Nagal #endif 102*c97857dbSAmit Nagal 103*c97857dbSAmit Nagal #define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT)) 104*c97857dbSAmit Nagal 105*c97857dbSAmit Nagal #ifndef MAX_MMAP_REGIONS 106*c97857dbSAmit Nagal #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 107*c97857dbSAmit Nagal #define MAX_MMAP_REGIONS 11 108*c97857dbSAmit Nagal #else 109*c97857dbSAmit Nagal #define MAX_MMAP_REGIONS 10 110*c97857dbSAmit Nagal #endif 111*c97857dbSAmit Nagal #endif 112*c97857dbSAmit Nagal 113*c97857dbSAmit Nagal #ifndef MAX_XLAT_TABLES 114*c97857dbSAmit Nagal #define MAX_XLAT_TABLES U(12) 115*c97857dbSAmit Nagal #endif 116*c97857dbSAmit Nagal 117*c97857dbSAmit Nagal #define CACHE_WRITEBACK_SHIFT U(6) 118*c97857dbSAmit Nagal #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 119*c97857dbSAmit Nagal 120*c97857dbSAmit Nagal #define PLAT_GICD_BASE_VALUE U(0xE2000000) 121*c97857dbSAmit Nagal #define PLAT_GICR_BASE_VALUE U(0xE2060000) 122*c97857dbSAmit Nagal 123*c97857dbSAmit Nagal /* 124*c97857dbSAmit Nagal * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 125*c97857dbSAmit Nagal * terminology. On a GICv2 system or mode, the lists will be merged and treated 126*c97857dbSAmit Nagal * as Group 0 interrupts. 127*c97857dbSAmit Nagal */ 128*c97857dbSAmit Nagal #define PLAT_IPI_IRQ 89 129*c97857dbSAmit Nagal #define PLAT_VERSAL_IPI_IRQ PLAT_IPI_IRQ 130*c97857dbSAmit Nagal 131*c97857dbSAmit Nagal #define PLAT_G1S_IRQ_PROPS(grp) \ 132*c97857dbSAmit Nagal INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 133*c97857dbSAmit Nagal GIC_INTR_CFG_LEVEL) 134*c97857dbSAmit Nagal 135*c97857dbSAmit Nagal #define PLAT_G0_IRQ_PROPS(grp) \ 136*c97857dbSAmit Nagal INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \ 137*c97857dbSAmit Nagal GIC_INTR_CFG_EDGE), \ 138*c97857dbSAmit Nagal 139*c97857dbSAmit Nagal #define IRQ_MAX 200U 140*c97857dbSAmit Nagal 141*c97857dbSAmit Nagal #endif /* PLATFORM_DEF_H */ 142