1*c97857dbSAmit Nagal /* 2*c97857dbSAmit Nagal * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. 3*c97857dbSAmit Nagal * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4*c97857dbSAmit Nagal * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5*c97857dbSAmit Nagal * 6*c97857dbSAmit Nagal * SPDX-License-Identifier: BSD-3-Clause 7*c97857dbSAmit Nagal */ 8*c97857dbSAmit Nagal 9*c97857dbSAmit Nagal #ifndef PLAT_PRIVATE_H 10*c97857dbSAmit Nagal #define PLAT_PRIVATE_H 11*c97857dbSAmit Nagal 12*c97857dbSAmit Nagal #include <bl31/interrupt_mgmt.h> 13*c97857dbSAmit Nagal #include <lib/xlat_tables/xlat_tables_v2.h> 14*c97857dbSAmit Nagal 15*c97857dbSAmit Nagal #define SPP_PSXC_MMI_V2_0 U(6) 16*c97857dbSAmit Nagal #define SPP_PSXC_MMI_V3_0 U(8) 17*c97857dbSAmit Nagal 18*c97857dbSAmit Nagal /* MMD */ 19*c97857dbSAmit Nagal #define SPP_PSXC_ISP_AIE_V2_0 U(3) 20*c97857dbSAmit Nagal #define SPP_PSXC_MMD_AIE_FRZ_EA U(4) 21*c97857dbSAmit Nagal #define SPP_PSXC_MMD_AIE_V3_0 U(5) 22*c97857dbSAmit Nagal 23*c97857dbSAmit Nagal typedef struct versal_intr_info_type_el3 { 24*c97857dbSAmit Nagal uint32_t id; 25*c97857dbSAmit Nagal interrupt_type_handler_t handler; 26*c97857dbSAmit Nagal } versal_intr_info_type_el3_t; 27*c97857dbSAmit Nagal 28*c97857dbSAmit Nagal void config_setup(void); 29*c97857dbSAmit Nagal uint32_t get_uart_clk(void); 30*c97857dbSAmit Nagal 31*c97857dbSAmit Nagal const mmap_region_t *plat_get_mmap(void); 32*c97857dbSAmit Nagal 33*c97857dbSAmit Nagal void plat_gic_driver_init(void); 34*c97857dbSAmit Nagal void plat_gic_init(void); 35*c97857dbSAmit Nagal void plat_gic_cpuif_enable(void); 36*c97857dbSAmit Nagal void plat_gic_cpuif_disable(void); 37*c97857dbSAmit Nagal void plat_gic_pcpu_init(void); 38*c97857dbSAmit Nagal void plat_gic_save(void); 39*c97857dbSAmit Nagal void plat_gic_resume(void); 40*c97857dbSAmit Nagal void plat_gic_redistif_on(void); 41*c97857dbSAmit Nagal void plat_gic_redistif_off(void); 42*c97857dbSAmit Nagal 43*c97857dbSAmit Nagal extern uint32_t cpu_clock, platform_id, platform_version; 44*c97857dbSAmit Nagal void board_detection(void); 45*c97857dbSAmit Nagal const char *board_name_decode(void); 46*c97857dbSAmit Nagal uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, 47*c97857dbSAmit Nagal uint64_t x4, void *cookie, void *handle, uint64_t flags); 48*c97857dbSAmit Nagal int32_t sip_svc_setup_init(void); 49*c97857dbSAmit Nagal /* 50*c97857dbSAmit Nagal * Register handler to specific GIC entrance 51*c97857dbSAmit Nagal * for INTR_TYPE_EL3 type of interrupt 52*c97857dbSAmit Nagal */ 53*c97857dbSAmit Nagal int request_intr_type_el3(uint32_t irq, interrupt_type_handler_t fiq_handler); 54*c97857dbSAmit Nagal 55*c97857dbSAmit Nagal #endif /* PLAT_PRIVATE_H */ 56