1c97857dbSAmit Nagal /* 2c97857dbSAmit Nagal * Copyright (c) 2022, Xilinx, Inc. All rights reserved. 3*414cf08bSSenthil Nathan Thangaraj * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 4c97857dbSAmit Nagal * 5c97857dbSAmit Nagal * SPDX-License-Identifier: BSD-3-Clause 6c97857dbSAmit Nagal */ 7c97857dbSAmit Nagal 8c97857dbSAmit Nagal /* 9c97857dbSAmit Nagal * Contains platform specific definitions of commonly used macros data types 10c97857dbSAmit Nagal * for PU Power Management. This file should be common for all PU's. 11c97857dbSAmit Nagal */ 12c97857dbSAmit Nagal 13c97857dbSAmit Nagal #ifndef PLAT_PM_COMMON_H 14c97857dbSAmit Nagal #define PLAT_PM_COMMON_H 15c97857dbSAmit Nagal 16c97857dbSAmit Nagal #include <stdint.h> 17c97857dbSAmit Nagal 18c97857dbSAmit Nagal #include <common/debug.h> 19c97857dbSAmit Nagal 20c97857dbSAmit Nagal #include "pm_defs.h" 21c97857dbSAmit Nagal 22c97857dbSAmit Nagal #define NON_SECURE_FLAG 1U 23c97857dbSAmit Nagal #define SECURE_FLAG 0U 24c97857dbSAmit Nagal 25*414cf08bSSenthil Nathan Thangaraj /* Processor core device IDs */ 26*414cf08bSSenthil Nathan Thangaraj #define PM_DEV_CLUSTER0_ACPU_0 (0x1810C0AFU) 27*414cf08bSSenthil Nathan Thangaraj #define PM_DEV_CLUSTER0_ACPU_1 (0x1810C0B0U) 28*414cf08bSSenthil Nathan Thangaraj 29*414cf08bSSenthil Nathan Thangaraj #define PM_DEV_CLUSTER1_ACPU_0 (0x1810C0B3U) 30*414cf08bSSenthil Nathan Thangaraj #define PM_DEV_CLUSTER1_ACPU_1 (0x1810C0B4U) 31*414cf08bSSenthil Nathan Thangaraj 32*414cf08bSSenthil Nathan Thangaraj #define PM_DEV_CLUSTER2_ACPU_0 (0x1810C0B7U) 33*414cf08bSSenthil Nathan Thangaraj #define PM_DEV_CLUSTER2_ACPU_1 (0x1810C0B8U) 34*414cf08bSSenthil Nathan Thangaraj 35*414cf08bSSenthil Nathan Thangaraj #define PM_DEV_CLUSTER3_ACPU_0 (0x1810C0BBU) 36*414cf08bSSenthil Nathan Thangaraj #define PM_DEV_CLUSTER3_ACPU_1 (0x1810C0BCU) 37*414cf08bSSenthil Nathan Thangaraj 38c97857dbSAmit Nagal #endif /* PLAT_PM_COMMON_H */ 39