1 /* 2 * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <common/debug.h> 10 #include <common/interrupt_props.h> 11 #include <drivers/arm/gicv3.h> 12 #include <lib/utils.h> 13 #include <plat/common/platform.h> 14 #include <platform_def.h> 15 16 #include <plat_private.h> 17 18 /****************************************************************************** 19 * The following functions are defined as weak to allow a platform to override 20 * the way the GICv3 driver is initialised and used. 21 *****************************************************************************/ 22 #pragma weak plat_gic_driver_init 23 #pragma weak plat_gic_init 24 #pragma weak plat_gic_cpuif_enable 25 #pragma weak plat_gic_cpuif_disable 26 #pragma weak plat_gic_pcpu_init 27 #pragma weak plat_gic_redistif_on 28 #pragma weak plat_gic_redistif_off 29 30 /* The GICv3 driver only needs to be initialized in EL3 */ 31 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 32 33 static const interrupt_prop_t _interrupt_props[] = { 34 PLAT_G1S_IRQ_PROPS(INTR_GROUP1S), 35 PLAT_G0_IRQ_PROPS(INTR_GROUP0) 36 }; 37 38 /* 39 * We save and restore the GICv3 context on system suspend. Allocate the 40 * data in the designated EL3 Secure carve-out memory. 41 */ 42 static gicv3_redist_ctx_t rdist_ctx __section("._el3_tzc_dram"); 43 static gicv3_dist_ctx_t dist_ctx __section("._el3_tzc_dram"); 44 45 /* 46 * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register 47 * to core position. 48 * 49 * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity 50 * values read from GICR_TYPER don't have an MT field. To reuse the same 51 * translation used for CPUs, we insert MT bit read from the PE's MPIDR into 52 * that read from GICR_TYPER. 53 * 54 * Assumptions: 55 * 56 * - All CPUs implemented in the system have MPIDR_EL1.MT bit set; 57 * - No CPUs implemented in the system use affinity level 3. 58 */ 59 static uint32_t _gicv3_mpidr_hash(u_register_t mpidr) 60 { 61 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); 62 return plat_core_pos_by_mpidr(mpidr); 63 } 64 65 static const gicv3_driver_data_t _gic_data __unused = { 66 .gicd_base = PLAT_GICD_BASE_VALUE, 67 .gicr_base = PLAT_GICR_BASE_VALUE, 68 .interrupt_props = _interrupt_props, 69 .interrupt_props_num = ARRAY_SIZE(_interrupt_props), 70 .rdistif_num = PLATFORM_CORE_COUNT, 71 .rdistif_base_addrs = rdistif_base_addrs, 72 .mpidr_to_core_pos = _gicv3_mpidr_hash 73 }; 74 75 void __init plat_gic_driver_init(void) 76 { 77 /* 78 * The GICv3 driver is initialized in EL3 and does not need 79 * to be initialized again in SEL1. This is because the S-EL1 80 * can use GIC system registers to manage interrupts and does 81 * not need GIC interface base addresses to be configured. 82 */ 83 #if IMAGE_BL31 84 gicv3_driver_init(&_gic_data); 85 #endif 86 } 87 88 /****************************************************************************** 89 * common helper to initialize the GIC. Only invoked by BL31 90 *****************************************************************************/ 91 void __init plat_gic_init(void) 92 { 93 gicv3_distif_init(); 94 gicv3_rdistif_init(plat_my_core_pos()); 95 gicv3_cpuif_enable(plat_my_core_pos()); 96 } 97 98 /****************************************************************************** 99 * common helper to enable the GIC CPU interface 100 *****************************************************************************/ 101 void plat_gic_cpuif_enable(void) 102 { 103 gicv3_cpuif_enable(plat_my_core_pos()); 104 } 105 106 /****************************************************************************** 107 * common helper to disable the GIC CPU interface 108 *****************************************************************************/ 109 void plat_gic_cpuif_disable(void) 110 { 111 gicv3_cpuif_disable(plat_my_core_pos()); 112 } 113 114 /****************************************************************************** 115 * common helper to initialize the per-cpu redistributor interface in GICv3 116 *****************************************************************************/ 117 void plat_gic_pcpu_init(void) 118 { 119 gicv3_rdistif_init(plat_my_core_pos()); 120 } 121 122 /****************************************************************************** 123 * common helpers to power GIC redistributor interface 124 *****************************************************************************/ 125 void plat_gic_redistif_on(void) 126 { 127 gicv3_rdistif_on(plat_my_core_pos()); 128 } 129 130 void plat_gic_redistif_off(void) 131 { 132 gicv3_rdistif_off(plat_my_core_pos()); 133 } 134 135 /****************************************************************************** 136 * common helper to save & restore the GICv3 on resume from system suspend 137 *****************************************************************************/ 138 void plat_gic_save(void) 139 { 140 /* 141 * If an ITS is available, save its context before 142 * the Redistributor using: 143 * gicv3_its_save_disable(gits_base, &its_ctx[i]) 144 * Additionnaly, an implementation-defined sequence may 145 * be required to save the whole ITS state. 146 */ 147 148 /* 149 * Save the GIC Redistributors and ITS contexts before the 150 * Distributor context. As we only handle SYSTEM SUSPEND API, 151 * we only need to save the context of the CPU that is issuing 152 * the SYSTEM SUSPEND call, i.e. the current CPU. 153 */ 154 gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx); 155 156 /* Save the GIC Distributor context */ 157 gicv3_distif_save(&dist_ctx); 158 159 /* 160 * From here, all the components of the GIC can be safely powered down 161 * as long as there is an alternate way to handle wakeup interrupt 162 * sources. 163 */ 164 } 165 166 void plat_gic_resume(void) 167 { 168 /* Restore the GIC Distributor context */ 169 gicv3_distif_init_restore(&dist_ctx); 170 171 /* 172 * Restore the GIC Redistributor and ITS contexts after the 173 * Distributor context. As we only handle SYSTEM SUSPEND API, 174 * we only need to restore the context of the CPU that issued 175 * the SYSTEM SUSPEND call. 176 */ 177 gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx); 178 179 /* 180 * If an ITS is available, restore its context after 181 * the Redistributor using: 182 * gicv3_its_restore(gits_base, &its_ctx[i]) 183 * An implementation-defined sequence may be required to 184 * restore the whole ITS state. The ITS must also be 185 * re-enabled after this sequence has been executed. 186 */ 187 } 188