1 /* 2 * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/dcc.h> 16 #include <drivers/arm/pl011.h> 17 #include <drivers/console.h> 18 #include <lib/cpus/cpu_ops.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_v2.h> 21 #include <plat/common/platform.h> 22 #include <plat_arm.h> 23 #include <plat_console.h> 24 #include <scmi.h> 25 26 #include <def.h> 27 #include <plat_fdt.h> 28 #include <plat_private.h> 29 #include <plat_startup.h> 30 #if TRANSFER_LIST 31 #include <plat_xfer_list.h> 32 #endif 33 #include <pm_api_sys.h> 34 #include <pm_client.h> 35 36 #include <plat_ocm_coherency.h> 37 38 static entry_point_info_t bl32_image_ep_info; 39 static entry_point_info_t bl33_image_ep_info; 40 41 /* 42 * Return a pointer to the 'entry_point_info' structure of the next image for 43 * the security state specified. BL33 corresponds to the non-secure image type 44 * while BL32 corresponds to the secure image type. A NULL pointer is returned 45 * if the image does not exist. 46 */ 47 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 48 { 49 assert(sec_state_is_valid(type)); 50 51 if (type == NON_SECURE) { 52 return &bl33_image_ep_info; 53 } 54 55 return &bl32_image_ep_info; 56 } 57 58 /* 59 * Set the build time defaults,if we can't find any config data. 60 */ 61 static inline void bl31_set_default_config(void) 62 { 63 bl32_image_ep_info.pc = BL32_BASE; 64 bl32_image_ep_info.spsr = arm_get_spsr(BL32_IMAGE_ID); 65 #if defined(SPD_opteed) 66 #if (TRANSFER_LIST == 0) 67 /* NS dtb addr passed to optee_os */ 68 bl32_image_ep_info.args.arg3 = XILINX_OF_BOARD_DTB_ADDR; 69 #endif 70 #endif 71 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 72 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, 73 DISABLE_ALL_EXCEPTIONS); 74 } 75 76 /* 77 * Perform any BL31 specific platform actions. Here is an opportunity to copy 78 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 79 * are lost (potentially). This needs to be done before the MMU is initialized 80 * so that the memory layout can be used while creating page tables. 81 */ 82 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 83 u_register_t arg2, u_register_t arg3) 84 { 85 (void)arg0; 86 (void)arg1; 87 (void)arg2; 88 (void)arg3; 89 uint32_t uart_clock; 90 #if (TRANSFER_LIST == 1) 91 int32_t rc; 92 bool tl_status = false; 93 #endif 94 95 board_detection(); 96 97 /* FIXME */ 98 switch (platform_id) { 99 case SPP: 100 switch (platform_version) { 101 case SPP_PSXC_MMI_V2_0: 102 cpu_clock = 770000; 103 break; 104 case SPP_PSXC_MMI_V3_0: 105 cpu_clock = 908000; 106 break; 107 default: 108 panic(); 109 } 110 break; 111 case SPP_MMD: 112 switch (platform_version) { 113 case SPP_PSXC_ISP_AIE_V2_0: 114 case SPP_PSXC_MMD_AIE_FRZ_EA: 115 case SPP_PSXC_MMD_AIE_V3_0: 116 cpu_clock = 760000; 117 break; 118 default: 119 panic(); 120 } 121 break; 122 case EMU: 123 case EMU_MMD: 124 cpu_clock = 112203; 125 break; 126 case QEMU: 127 case SILICON: 128 cpu_clock = 100000000; 129 break; 130 default: 131 panic(); 132 } 133 #if (TRANSFER_LIST == 1) 134 tl_status = populate_data_from_xfer_list(); 135 if (tl_status != true) { 136 WARN("Invalid transfer list\n"); 137 } 138 #endif 139 140 uart_clock = get_uart_clk(); 141 142 /* Initialize the platform config for future decision making */ 143 config_setup(); 144 145 setup_console(); 146 147 if (IS_TFA_IN_OCM(BL31_BASE) && (check_ocm_coherency() < 0)) { 148 NOTICE("OCM coherency check not supported\n"); 149 } 150 151 NOTICE("TF-A running on %s v%d.%d, RTL v%d.%d, PS v%d.%d, PMC v%d.%d\n", 152 board_name_decode(), 153 (platform_version >> 1), platform_version % 10U, 154 (rtlversion >> 1), rtlversion % 10U, 155 (psversion >> 1), psversion % 10U, 156 (pmcversion >> 1), pmcversion % 10U); 157 158 /* 159 * Do initial security configuration to allow DRAM/device access. On 160 * Base only DRAM security is programmable (via TrustZone), but 161 * other platforms might have more programmable security devices 162 * present. 163 */ 164 165 /* Populate common information for BL32 and BL33 */ 166 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 167 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 168 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 169 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 170 171 #if (TRANSFER_LIST == 1) 172 rc = transfer_list_populate_ep_info(&bl32_image_ep_info, &bl33_image_ep_info); 173 if (rc == TL_OPS_NON || rc == TL_OPS_CUS) { 174 NOTICE("BL31: TL not found, using default config\n"); 175 bl31_set_default_config(); 176 } 177 #else 178 bl31_set_default_config(); 179 #endif 180 181 long rev_var = cpu_get_rev_var(); 182 183 INFO("CPU Revision = 0x%lx\n", rev_var); 184 INFO("cpu_clock = %dHz, uart_clock = %dHz\n", cpu_clock, uart_clock); 185 NOTICE("BL31: Executing from 0x%x\n", BL31_BASE); 186 #if (defined(SPD_tspd) || defined(SPD_opteed)) 187 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 188 #endif /* SPD_tspd || SPD_opteed */ 189 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 190 191 } 192 193 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 194 195 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 196 { 197 static uint32_t index; 198 uint32_t i; 199 int32_t ret = 0; 200 201 /* Validate 'handler' and 'id' parameters */ 202 if ((handler == NULL) || (index >= MAX_INTR_EL3)) { 203 ret = -EINVAL; 204 goto exit_label; 205 } 206 207 /* Check if a handler has already been registered */ 208 for (i = 0; i < index; i++) { 209 if (id == type_el3_interrupt_table[i].id) { 210 ret = -EALREADY; 211 goto exit_label; 212 } 213 } 214 215 type_el3_interrupt_table[index].id = id; 216 type_el3_interrupt_table[index].handler = handler; 217 218 index++; 219 220 exit_label: 221 return ret; 222 } 223 224 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 225 void *handle, void *cookie) 226 { 227 (void)id; 228 uint32_t intr_id; 229 uint32_t i; 230 interrupt_type_handler_t handler = NULL; 231 232 intr_id = plat_ic_get_pending_interrupt_id(); 233 234 for (i = 0; i < MAX_INTR_EL3; i++) { 235 if (intr_id == type_el3_interrupt_table[i].id) { 236 handler = type_el3_interrupt_table[i].handler; 237 } 238 } 239 240 if (handler != NULL) { 241 (void)handler(intr_id, flags, handle, cookie); 242 } 243 244 return 0; 245 } 246 247 void bl31_platform_setup(void) 248 { 249 prepare_dtb(); 250 251 /* Initialize the gic cpu and distributor interfaces */ 252 plat_gic_driver_init(); 253 plat_gic_init(); 254 255 if (platform_id != EMU) { 256 init_scmi_server(); 257 } 258 } 259 260 void bl31_plat_runtime_setup(void) 261 { 262 uint32_t flags = 0; 263 int32_t rc; 264 uint32_t rre_ret = 0; 265 266 set_interrupt_rm_flag(flags, NON_SECURE); 267 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 268 rdo_el3_interrupt_handler, flags); 269 if (rc != 0) { 270 panic(); 271 } 272 273 /* Instead of calling for each time fill in structure early. */ 274 rre_ret = retrieve_reserved_entries(); 275 276 if (rre_ret != 0) { 277 INFO("Runtime FDT reserve node retreival failed"); 278 } 279 280 console_switch_state(CONSOLE_FLAG_RUNTIME); 281 } 282 283 /* 284 * Perform the very early platform specific architectural setup here. 285 */ 286 void bl31_plat_arch_setup(void) 287 { 288 const mmap_region_t bl_regions[] = { 289 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 290 MT_MEMORY | MT_RW | MT_SECURE), 291 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 292 MT_CODE | MT_SECURE), 293 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 294 MT_RO_DATA | MT_SECURE), 295 MAP_REGION_FLAT(SMT_BUFFER_BASE, 0x1000, 296 MT_DEVICE | MT_RW | MT_NON_CACHEABLE | MT_EXECUTE_NEVER | MT_NS), 297 {0} 298 }; 299 300 setup_page_tables(bl_regions, plat_get_mmap()); 301 enable_mmu(0); 302 } 303