1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/dcc.h> 16 #include <drivers/arm/pl011.h> 17 #include <drivers/console.h> 18 #include <lib/cpus/cpu_ops.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_v2.h> 21 #include <plat/common/platform.h> 22 #include <plat_arm.h> 23 #include <plat_console.h> 24 #include <scmi.h> 25 26 #include <def.h> 27 #include <plat_fdt.h> 28 #include <plat_private.h> 29 #include <plat_startup.h> 30 #include <plat_xfer_list.h> 31 #include <pm_api_sys.h> 32 #include <pm_client.h> 33 34 static entry_point_info_t bl32_image_ep_info; 35 static entry_point_info_t bl33_image_ep_info; 36 37 /* 38 * Return a pointer to the 'entry_point_info' structure of the next image for 39 * the security state specified. BL33 corresponds to the non-secure image type 40 * while BL32 corresponds to the secure image type. A NULL pointer is returned 41 * if the image does not exist. 42 */ 43 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 44 { 45 assert(sec_state_is_valid(type)); 46 47 if (type == NON_SECURE) { 48 return &bl33_image_ep_info; 49 } 50 51 return &bl32_image_ep_info; 52 } 53 54 /* 55 * Set the build time defaults,if we can't find any config data. 56 */ 57 static inline void bl31_set_default_config(void) 58 { 59 bl32_image_ep_info.pc = BL32_BASE; 60 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 61 #if defined(SPD_opteed) 62 /* NS dtb addr passed to optee_os */ 63 bl32_image_ep_info.args.arg3 = XILINX_OF_BOARD_DTB_ADDR; 64 #endif 65 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 66 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, 67 DISABLE_ALL_EXCEPTIONS); 68 } 69 70 /* 71 * Perform any BL31 specific platform actions. Here is an opportunity to copy 72 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 73 * are lost (potentially). This needs to be done before the MMU is initialized 74 * so that the memory layout can be used while creating page tables. 75 */ 76 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 77 u_register_t arg2, u_register_t arg3) 78 { 79 (void)arg0; 80 (void)arg1; 81 (void)arg2; 82 (void)arg3; 83 uint32_t uart_clock; 84 int32_t rc; 85 86 board_detection(); 87 88 /* FIXME */ 89 switch (platform_id) { 90 case SPP: 91 switch (platform_version) { 92 case SPP_PSXC_MMI_V2_0: 93 cpu_clock = 770000; 94 break; 95 case SPP_PSXC_MMI_V3_0: 96 cpu_clock = 908000; 97 break; 98 default: 99 panic(); 100 } 101 break; 102 case SPP_MMD: 103 switch (platform_version) { 104 case SPP_PSXC_ISP_AIE_V2_0: 105 case SPP_PSXC_MMD_AIE_FRZ_EA: 106 case SPP_PSXC_MMD_AIE_V3_0: 107 cpu_clock = 760000; 108 break; 109 default: 110 panic(); 111 } 112 break; 113 case EMU: 114 case EMU_MMD: 115 cpu_clock = 112203; 116 break; 117 case QEMU: 118 /* Random values now */ 119 cpu_clock = 3333333; 120 break; 121 case SILICON: 122 cpu_clock = 100000000; 123 break; 124 default: 125 panic(); 126 } 127 128 uart_clock = get_uart_clk(); 129 130 /* Initialize the platform config for future decision making */ 131 config_setup(); 132 133 setup_console(); 134 135 NOTICE("TF-A running on %s v%d.%d, RTL v%d.%d, PS v%d.%d, PMC v%d.%d\n", 136 board_name_decode(), 137 (platform_version >> 1), platform_version % 10U, 138 (rtlversion >> 1), rtlversion % 10U, 139 (psversion >> 1), psversion % 10U, 140 (pmcversion >> 1), pmcversion % 10U); 141 142 /* 143 * Do initial security configuration to allow DRAM/device access. On 144 * Base only DRAM security is programmable (via TrustZone), but 145 * other platforms might have more programmable security devices 146 * present. 147 */ 148 149 /* Populate common information for BL32 and BL33 */ 150 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 151 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 152 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 153 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 154 155 rc = transfer_list_populate_ep_info(&bl32_image_ep_info, &bl33_image_ep_info); 156 if (rc == TL_OPS_NON || rc == TL_OPS_CUS) { 157 NOTICE("BL31: TL not found, using default config\n"); 158 bl31_set_default_config(); 159 } 160 161 long rev_var = cpu_get_rev_var(); 162 163 INFO("CPU Revision = 0x%lx\n", rev_var); 164 INFO("cpu_clock = %dHz, uart_clock = %dHz\n", cpu_clock, uart_clock); 165 NOTICE("BL31: Executing from 0x%x\n", BL31_BASE); 166 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 167 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 168 169 } 170 171 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 172 173 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 174 { 175 static uint32_t index; 176 uint32_t i; 177 int32_t ret = 0; 178 179 /* Validate 'handler' and 'id' parameters */ 180 if ((handler == NULL) || (index >= MAX_INTR_EL3)) { 181 ret = -EINVAL; 182 goto exit_label; 183 } 184 185 /* Check if a handler has already been registered */ 186 for (i = 0; i < index; i++) { 187 if (id == type_el3_interrupt_table[i].id) { 188 ret = -EALREADY; 189 goto exit_label; 190 } 191 } 192 193 type_el3_interrupt_table[index].id = id; 194 type_el3_interrupt_table[index].handler = handler; 195 196 index++; 197 198 exit_label: 199 return ret; 200 } 201 202 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 203 void *handle, void *cookie) 204 { 205 (void)id; 206 uint32_t intr_id; 207 uint32_t i; 208 interrupt_type_handler_t handler = NULL; 209 210 intr_id = plat_ic_get_pending_interrupt_id(); 211 212 for (i = 0; i < MAX_INTR_EL3; i++) { 213 if (intr_id == type_el3_interrupt_table[i].id) { 214 handler = type_el3_interrupt_table[i].handler; 215 } 216 } 217 218 if (handler != NULL) { 219 (void)handler(intr_id, flags, handle, cookie); 220 } 221 222 return 0; 223 } 224 225 void bl31_platform_setup(void) 226 { 227 prepare_dtb(); 228 229 /* Initialize the gic cpu and distributor interfaces */ 230 plat_gic_driver_init(); 231 plat_gic_init(); 232 233 if (platform_id != EMU) { 234 init_scmi_server(); 235 } 236 } 237 238 void bl31_plat_runtime_setup(void) 239 { 240 uint32_t flags = 0; 241 int32_t rc; 242 243 set_interrupt_rm_flag(flags, NON_SECURE); 244 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 245 rdo_el3_interrupt_handler, flags); 246 if (rc != 0) { 247 panic(); 248 } 249 250 console_switch_state(CONSOLE_FLAG_RUNTIME); 251 } 252 253 /* 254 * Perform the very early platform specific architectural setup here. 255 */ 256 void bl31_plat_arch_setup(void) 257 { 258 const mmap_region_t bl_regions[] = { 259 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 260 MT_MEMORY | MT_RW | MT_SECURE), 261 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 262 MT_CODE | MT_SECURE), 263 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 264 MT_RO_DATA | MT_SECURE), 265 MAP_REGION_FLAT(SMT_BUFFER_BASE, 0x1000, 266 MT_DEVICE | MT_RW | MT_NON_CACHEABLE | MT_EXECUTE_NEVER | MT_NS), 267 {0} 268 }; 269 270 setup_page_tables(bl_regions, plat_get_mmap()); 271 enable_mmu(0); 272 } 273