1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/dcc.h> 16 #include <drivers/arm/pl011.h> 17 #include <drivers/console.h> 18 #include <lib/cpus/cpu_ops.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_v2.h> 21 #include <plat/common/platform.h> 22 #include <plat_arm.h> 23 #include <scmi.h> 24 25 #include <def.h> 26 #include <plat_fdt.h> 27 #include <plat_private.h> 28 #include <plat_startup.h> 29 #include <pm_api_sys.h> 30 #include <pm_client.h> 31 32 static entry_point_info_t bl32_image_ep_info; 33 static entry_point_info_t bl33_image_ep_info; 34 35 /* 36 * Return a pointer to the 'entry_point_info' structure of the next image for 37 * the security state specified. BL33 corresponds to the non-secure image type 38 * while BL32 corresponds to the secure image type. A NULL pointer is returned 39 * if the image does not exist. 40 */ 41 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 42 { 43 assert(sec_state_is_valid(type)); 44 45 if (type == NON_SECURE) { 46 return &bl33_image_ep_info; 47 } 48 49 return &bl32_image_ep_info; 50 } 51 52 /* 53 * Set the build time defaults,if we can't find any config data. 54 */ 55 static inline void bl31_set_default_config(void) 56 { 57 bl32_image_ep_info.pc = BL32_BASE; 58 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 59 #if defined(SPD_opteed) 60 /* NS dtb addr passed to optee_os */ 61 bl32_image_ep_info.args.arg3 = XILINX_OF_BOARD_DTB_ADDR; 62 #endif 63 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 64 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 65 DISABLE_ALL_EXCEPTIONS); 66 } 67 68 /* 69 * Perform any BL31 specific platform actions. Here is an opportunity to copy 70 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 71 * are lost (potentially). This needs to be done before the MMU is initialized 72 * so that the memory layout can be used while creating page tables. 73 */ 74 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 75 u_register_t arg2, u_register_t arg3) 76 { 77 uint32_t uart_clock; 78 int32_t rc; 79 80 board_detection(); 81 82 /* FIXME */ 83 switch (platform_id) { 84 case SPP: 85 switch (platform_version) { 86 case SPP_PSXC_MMI_V2_0: 87 cpu_clock = 770000; 88 break; 89 case SPP_PSXC_MMI_V3_0: 90 cpu_clock = 908000; 91 break; 92 default: 93 panic(); 94 } 95 break; 96 case SPP_MMD: 97 switch (platform_version) { 98 case SPP_PSXC_ISP_AIE_V2_0: 99 case SPP_PSXC_MMD_AIE_FRZ_EA: 100 case SPP_PSXC_MMD_AIE_V3_0: 101 cpu_clock = 760000; 102 break; 103 default: 104 panic(); 105 } 106 break; 107 case EMU: 108 case EMU_MMD: 109 cpu_clock = 112203; 110 break; 111 case QEMU: 112 /* Random values now */ 113 cpu_clock = 3333333; 114 break; 115 case SILICON: 116 cpu_clock = 100000000; 117 break; 118 default: 119 panic(); 120 } 121 122 uart_clock = get_uart_clk(); 123 124 if (CONSOLE_IS(pl011_0) || CONSOLE_IS(pl011_1)) { 125 static console_t _runtime_console; 126 127 /* Initialize the console to provide early debug support */ 128 rc = console_pl011_register(UART_BASE, uart_clock, 129 UART_BAUDRATE, 130 &_runtime_console); 131 if (rc == 0) { 132 panic(); 133 } 134 135 console_set_scope(&_runtime_console, CONSOLE_FLAG_BOOT | 136 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); 137 } else if (CONSOLE_IS(dcc)) { 138 /* Initialize the dcc console for debug. 139 * dcc is over jtag and does not configures uart0 or uart1. 140 */ 141 rc = console_dcc_register(); 142 if (rc == 0) { 143 panic(); 144 } 145 } else { 146 /* Making MISRA C 2012 15.7 compliant */ 147 } 148 149 NOTICE("TF-A running on %s %d.%d\n", board_name_decode(), 150 platform_version / 10U, platform_version % 10U); 151 152 /* Initialize the platform config for future decision making */ 153 config_setup(); 154 155 /* 156 * Do initial security configuration to allow DRAM/device access. On 157 * Base only DRAM security is programmable (via TrustZone), but 158 * other platforms might have more programmable security devices 159 * present. 160 */ 161 162 /* Populate common information for BL32 and BL33 */ 163 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 164 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 165 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 166 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 167 bl31_set_default_config(); 168 169 long rev_var = cpu_get_rev_var(); 170 171 INFO("CPU Revision = 0x%lx\n", rev_var); 172 INFO("cpu_clock = %dHz, uart_clock = %dHz\n", cpu_clock, uart_clock); 173 NOTICE("BL31: Executing from 0x%x\n", BL31_BASE); 174 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 175 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 176 177 } 178 179 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 180 181 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 182 { 183 static uint32_t index; 184 uint32_t i; 185 186 /* Validate 'handler' and 'id' parameters */ 187 if (handler == NULL || index >= MAX_INTR_EL3) { 188 return -EINVAL; 189 } 190 191 /* Check if a handler has already been registered */ 192 for (i = 0; i < index; i++) { 193 if (id == type_el3_interrupt_table[i].id) { 194 return -EALREADY; 195 } 196 } 197 198 type_el3_interrupt_table[index].id = id; 199 type_el3_interrupt_table[index].handler = handler; 200 201 index++; 202 203 return 0; 204 } 205 206 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 207 void *handle, void *cookie) 208 { 209 uint32_t intr_id; 210 uint32_t i; 211 interrupt_type_handler_t handler = NULL; 212 213 intr_id = plat_ic_get_pending_interrupt_id(); 214 215 for (i = 0; i < MAX_INTR_EL3; i++) { 216 if (intr_id == type_el3_interrupt_table[i].id) { 217 handler = type_el3_interrupt_table[i].handler; 218 } 219 } 220 221 if (handler != NULL) { 222 (void)handler(intr_id, flags, handle, cookie); 223 } 224 225 return 0; 226 } 227 228 void bl31_platform_setup(void) 229 { 230 prepare_dtb(); 231 232 /* Initialize the gic cpu and distributor interfaces */ 233 plat_gic_driver_init(); 234 plat_gic_init(); 235 236 if (platform_id != EMU) { 237 init_scmi_server(); 238 } 239 } 240 241 void bl31_plat_runtime_setup(void) 242 { 243 uint64_t flags = 0; 244 int32_t rc; 245 246 set_interrupt_rm_flag(flags, NON_SECURE); 247 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 248 rdo_el3_interrupt_handler, flags); 249 if (rc != 0) { 250 panic(); 251 } 252 } 253 254 /* 255 * Perform the very early platform specific architectural setup here. 256 */ 257 void bl31_plat_arch_setup(void) 258 { 259 const mmap_region_t bl_regions[] = { 260 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 261 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, 262 MT_MEMORY | MT_RW | MT_NS), 263 #endif 264 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 265 MT_MEMORY | MT_RW | MT_SECURE), 266 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 267 MT_CODE | MT_SECURE), 268 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 269 MT_RO_DATA | MT_SECURE), 270 MAP_REGION_FLAT(SMT_BUFFER_BASE, 0x1000, 271 MT_DEVICE | MT_RW | MT_NON_CACHEABLE | MT_EXECUTE_NEVER | MT_NS), 272 {0} 273 }; 274 275 setup_page_tables(bl_regions, plat_get_mmap()); 276 enable_mmu(0); 277 } 278