1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/dcc.h> 16 #include <drivers/arm/pl011.h> 17 #include <drivers/console.h> 18 #include <lib/cpus/cpu_ops.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_v2.h> 21 #include <plat/common/platform.h> 22 #include <plat_arm.h> 23 #include <plat_console.h> 24 #include <scmi.h> 25 26 #include <def.h> 27 #include <plat_fdt.h> 28 #include <plat_private.h> 29 #include <plat_startup.h> 30 #include <pm_api_sys.h> 31 #include <pm_client.h> 32 33 static entry_point_info_t bl32_image_ep_info; 34 static entry_point_info_t bl33_image_ep_info; 35 36 /* 37 * Return a pointer to the 'entry_point_info' structure of the next image for 38 * the security state specified. BL33 corresponds to the non-secure image type 39 * while BL32 corresponds to the secure image type. A NULL pointer is returned 40 * if the image does not exist. 41 */ 42 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 43 { 44 assert(sec_state_is_valid(type)); 45 46 if (type == NON_SECURE) { 47 return &bl33_image_ep_info; 48 } 49 50 return &bl32_image_ep_info; 51 } 52 53 /* 54 * Set the build time defaults,if we can't find any config data. 55 */ 56 static inline void bl31_set_default_config(void) 57 { 58 bl32_image_ep_info.pc = BL32_BASE; 59 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 60 #if defined(SPD_opteed) 61 /* NS dtb addr passed to optee_os */ 62 bl32_image_ep_info.args.arg3 = XILINX_OF_BOARD_DTB_ADDR; 63 #endif 64 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 65 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 66 DISABLE_ALL_EXCEPTIONS); 67 } 68 69 /* 70 * Perform any BL31 specific platform actions. Here is an opportunity to copy 71 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 72 * are lost (potentially). This needs to be done before the MMU is initialized 73 * so that the memory layout can be used while creating page tables. 74 */ 75 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 76 u_register_t arg2, u_register_t arg3) 77 { 78 uint32_t uart_clock; 79 80 board_detection(); 81 82 /* FIXME */ 83 switch (platform_id) { 84 case SPP: 85 switch (platform_version) { 86 case SPP_PSXC_MMI_V2_0: 87 cpu_clock = 770000; 88 break; 89 case SPP_PSXC_MMI_V3_0: 90 cpu_clock = 908000; 91 break; 92 default: 93 panic(); 94 } 95 break; 96 case SPP_MMD: 97 switch (platform_version) { 98 case SPP_PSXC_ISP_AIE_V2_0: 99 case SPP_PSXC_MMD_AIE_FRZ_EA: 100 case SPP_PSXC_MMD_AIE_V3_0: 101 cpu_clock = 760000; 102 break; 103 default: 104 panic(); 105 } 106 break; 107 case EMU: 108 case EMU_MMD: 109 cpu_clock = 112203; 110 break; 111 case QEMU: 112 /* Random values now */ 113 cpu_clock = 3333333; 114 break; 115 case SILICON: 116 cpu_clock = 100000000; 117 break; 118 default: 119 panic(); 120 } 121 122 uart_clock = get_uart_clk(); 123 124 setup_console(); 125 126 NOTICE("TF-A running on %s %d.%d\n", board_name_decode(), 127 platform_version / 10U, platform_version % 10U); 128 129 /* Initialize the platform config for future decision making */ 130 config_setup(); 131 132 /* 133 * Do initial security configuration to allow DRAM/device access. On 134 * Base only DRAM security is programmable (via TrustZone), but 135 * other platforms might have more programmable security devices 136 * present. 137 */ 138 139 /* Populate common information for BL32 and BL33 */ 140 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 141 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 142 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 143 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 144 bl31_set_default_config(); 145 146 long rev_var = cpu_get_rev_var(); 147 148 INFO("CPU Revision = 0x%lx\n", rev_var); 149 INFO("cpu_clock = %dHz, uart_clock = %dHz\n", cpu_clock, uart_clock); 150 NOTICE("BL31: Executing from 0x%x\n", BL31_BASE); 151 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 152 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 153 154 } 155 156 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 157 158 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 159 { 160 static uint32_t index; 161 uint32_t i; 162 163 /* Validate 'handler' and 'id' parameters */ 164 if (handler == NULL || index >= MAX_INTR_EL3) { 165 return -EINVAL; 166 } 167 168 /* Check if a handler has already been registered */ 169 for (i = 0; i < index; i++) { 170 if (id == type_el3_interrupt_table[i].id) { 171 return -EALREADY; 172 } 173 } 174 175 type_el3_interrupt_table[index].id = id; 176 type_el3_interrupt_table[index].handler = handler; 177 178 index++; 179 180 return 0; 181 } 182 183 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 184 void *handle, void *cookie) 185 { 186 uint32_t intr_id; 187 uint32_t i; 188 interrupt_type_handler_t handler = NULL; 189 190 intr_id = plat_ic_get_pending_interrupt_id(); 191 192 for (i = 0; i < MAX_INTR_EL3; i++) { 193 if (intr_id == type_el3_interrupt_table[i].id) { 194 handler = type_el3_interrupt_table[i].handler; 195 } 196 } 197 198 if (handler != NULL) { 199 (void)handler(intr_id, flags, handle, cookie); 200 } 201 202 return 0; 203 } 204 205 void bl31_platform_setup(void) 206 { 207 prepare_dtb(); 208 209 /* Initialize the gic cpu and distributor interfaces */ 210 plat_gic_driver_init(); 211 plat_gic_init(); 212 213 if (platform_id != EMU) { 214 init_scmi_server(); 215 } 216 } 217 218 void bl31_plat_runtime_setup(void) 219 { 220 uint64_t flags = 0; 221 int32_t rc; 222 223 set_interrupt_rm_flag(flags, NON_SECURE); 224 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 225 rdo_el3_interrupt_handler, flags); 226 if (rc != 0) { 227 panic(); 228 } 229 230 console_switch_state(CONSOLE_FLAG_RUNTIME); 231 } 232 233 /* 234 * Perform the very early platform specific architectural setup here. 235 */ 236 void bl31_plat_arch_setup(void) 237 { 238 const mmap_region_t bl_regions[] = { 239 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 240 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, 241 MT_MEMORY | MT_RW | MT_NS), 242 #endif 243 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 244 MT_MEMORY | MT_RW | MT_SECURE), 245 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 246 MT_CODE | MT_SECURE), 247 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 248 MT_RO_DATA | MT_SECURE), 249 MAP_REGION_FLAT(SMT_BUFFER_BASE, 0x1000, 250 MT_DEVICE | MT_RW | MT_NON_CACHEABLE | MT_EXECUTE_NEVER | MT_NS), 251 {0} 252 }; 253 254 setup_page_tables(bl_regions, plat_get_mmap()); 255 enable_mmu(0); 256 } 257