1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/dcc.h> 16 #include <drivers/arm/pl011.h> 17 #include <drivers/console.h> 18 #include <lib/cpus/cpu_ops.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_v2.h> 21 #include <plat/common/platform.h> 22 #include <plat_arm.h> 23 #include <plat_console.h> 24 #include <scmi.h> 25 26 #include <def.h> 27 #include <plat_fdt.h> 28 #include <plat_private.h> 29 #include <plat_startup.h> 30 #include <plat_xfer_list.h> 31 #include <pm_api_sys.h> 32 #include <pm_client.h> 33 34 static entry_point_info_t bl32_image_ep_info; 35 static entry_point_info_t bl33_image_ep_info; 36 37 /* 38 * Return a pointer to the 'entry_point_info' structure of the next image for 39 * the security state specified. BL33 corresponds to the non-secure image type 40 * while BL32 corresponds to the secure image type. A NULL pointer is returned 41 * if the image does not exist. 42 */ 43 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 44 { 45 assert(sec_state_is_valid(type)); 46 47 if (type == NON_SECURE) { 48 return &bl33_image_ep_info; 49 } 50 51 return &bl32_image_ep_info; 52 } 53 54 /* 55 * Set the build time defaults,if we can't find any config data. 56 */ 57 static inline void bl31_set_default_config(void) 58 { 59 bl32_image_ep_info.pc = BL32_BASE; 60 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 61 #if defined(SPD_opteed) 62 #if (TRANSFER_LIST == 0) 63 /* NS dtb addr passed to optee_os */ 64 bl32_image_ep_info.args.arg3 = XILINX_OF_BOARD_DTB_ADDR; 65 #endif 66 #endif 67 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 68 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, 69 DISABLE_ALL_EXCEPTIONS); 70 } 71 72 /* 73 * Perform any BL31 specific platform actions. Here is an opportunity to copy 74 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 75 * are lost (potentially). This needs to be done before the MMU is initialized 76 * so that the memory layout can be used while creating page tables. 77 */ 78 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 79 u_register_t arg2, u_register_t arg3) 80 { 81 (void)arg0; 82 (void)arg1; 83 (void)arg2; 84 (void)arg3; 85 uint32_t uart_clock; 86 #if (TRANSFER_LIST == 1) 87 int32_t rc; 88 bool tl_status = false; 89 #endif 90 91 board_detection(); 92 93 /* FIXME */ 94 switch (platform_id) { 95 case SPP: 96 switch (platform_version) { 97 case SPP_PSXC_MMI_V2_0: 98 cpu_clock = 770000; 99 break; 100 case SPP_PSXC_MMI_V3_0: 101 cpu_clock = 908000; 102 break; 103 default: 104 panic(); 105 } 106 break; 107 case SPP_MMD: 108 switch (platform_version) { 109 case SPP_PSXC_ISP_AIE_V2_0: 110 case SPP_PSXC_MMD_AIE_FRZ_EA: 111 case SPP_PSXC_MMD_AIE_V3_0: 112 cpu_clock = 760000; 113 break; 114 default: 115 panic(); 116 } 117 break; 118 case EMU: 119 case EMU_MMD: 120 cpu_clock = 112203; 121 break; 122 case QEMU: 123 /* Random values now */ 124 cpu_clock = 3333333; 125 break; 126 case SILICON: 127 cpu_clock = 100000000; 128 break; 129 default: 130 panic(); 131 } 132 #if (TRANSFER_LIST == 1) 133 tl_status = populate_data_from_xfer_list(); 134 if (tl_status != true) { 135 WARN("Invalid transfer list\n"); 136 } 137 #endif 138 139 uart_clock = get_uart_clk(); 140 141 /* Initialize the platform config for future decision making */ 142 config_setup(); 143 144 setup_console(); 145 146 NOTICE("TF-A running on %s v%d.%d, RTL v%d.%d, PS v%d.%d, PMC v%d.%d\n", 147 board_name_decode(), 148 (platform_version >> 1), platform_version % 10U, 149 (rtlversion >> 1), rtlversion % 10U, 150 (psversion >> 1), psversion % 10U, 151 (pmcversion >> 1), pmcversion % 10U); 152 153 /* 154 * Do initial security configuration to allow DRAM/device access. On 155 * Base only DRAM security is programmable (via TrustZone), but 156 * other platforms might have more programmable security devices 157 * present. 158 */ 159 160 /* Populate common information for BL32 and BL33 */ 161 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 162 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 163 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 164 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 165 166 #if (TRANSFER_LIST == 1) 167 rc = transfer_list_populate_ep_info(&bl32_image_ep_info, &bl33_image_ep_info); 168 if (rc == TL_OPS_NON || rc == TL_OPS_CUS) { 169 NOTICE("BL31: TL not found, using default config\n"); 170 bl31_set_default_config(); 171 } 172 #else 173 bl31_set_default_config(); 174 #endif 175 176 long rev_var = cpu_get_rev_var(); 177 178 INFO("CPU Revision = 0x%lx\n", rev_var); 179 INFO("cpu_clock = %dHz, uart_clock = %dHz\n", cpu_clock, uart_clock); 180 NOTICE("BL31: Executing from 0x%x\n", BL31_BASE); 181 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 182 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 183 184 } 185 186 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 187 188 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 189 { 190 static uint32_t index; 191 uint32_t i; 192 int32_t ret = 0; 193 194 /* Validate 'handler' and 'id' parameters */ 195 if ((handler == NULL) || (index >= MAX_INTR_EL3)) { 196 ret = -EINVAL; 197 goto exit_label; 198 } 199 200 /* Check if a handler has already been registered */ 201 for (i = 0; i < index; i++) { 202 if (id == type_el3_interrupt_table[i].id) { 203 ret = -EALREADY; 204 goto exit_label; 205 } 206 } 207 208 type_el3_interrupt_table[index].id = id; 209 type_el3_interrupt_table[index].handler = handler; 210 211 index++; 212 213 exit_label: 214 return ret; 215 } 216 217 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 218 void *handle, void *cookie) 219 { 220 (void)id; 221 uint32_t intr_id; 222 uint32_t i; 223 interrupt_type_handler_t handler = NULL; 224 225 intr_id = plat_ic_get_pending_interrupt_id(); 226 227 for (i = 0; i < MAX_INTR_EL3; i++) { 228 if (intr_id == type_el3_interrupt_table[i].id) { 229 handler = type_el3_interrupt_table[i].handler; 230 } 231 } 232 233 if (handler != NULL) { 234 (void)handler(intr_id, flags, handle, cookie); 235 } 236 237 return 0; 238 } 239 240 void bl31_platform_setup(void) 241 { 242 prepare_dtb(); 243 244 /* Initialize the gic cpu and distributor interfaces */ 245 plat_gic_driver_init(); 246 plat_gic_init(); 247 248 if (platform_id != EMU) { 249 init_scmi_server(); 250 } 251 } 252 253 void bl31_plat_runtime_setup(void) 254 { 255 uint32_t flags = 0; 256 int32_t rc; 257 258 set_interrupt_rm_flag(flags, NON_SECURE); 259 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 260 rdo_el3_interrupt_handler, flags); 261 if (rc != 0) { 262 panic(); 263 } 264 265 console_switch_state(CONSOLE_FLAG_RUNTIME); 266 } 267 268 /* 269 * Perform the very early platform specific architectural setup here. 270 */ 271 void bl31_plat_arch_setup(void) 272 { 273 const mmap_region_t bl_regions[] = { 274 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 275 MT_MEMORY | MT_RW | MT_SECURE), 276 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 277 MT_CODE | MT_SECURE), 278 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 279 MT_RO_DATA | MT_SECURE), 280 MAP_REGION_FLAT(SMT_BUFFER_BASE, 0x1000, 281 MT_DEVICE | MT_RW | MT_NON_CACHEABLE | MT_EXECUTE_NEVER | MT_NS), 282 {0} 283 }; 284 285 setup_page_tables(bl_regions, plat_get_mmap()); 286 enable_mmu(0); 287 } 288