1 /* 2 * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/dcc.h> 16 #include <drivers/arm/pl011.h> 17 #include <drivers/console.h> 18 #include <lib/cpus/cpu_ops.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_v2.h> 21 #include <plat/common/platform.h> 22 #include <plat_arm.h> 23 #include <plat_console.h> 24 #include <scmi.h> 25 26 #include <custom_svc.h> 27 #include <def.h> 28 #include <plat_fdt.h> 29 #include <plat_private.h> 30 #include <plat_startup.h> 31 #if TRANSFER_LIST 32 #include <plat_xfer_list.h> 33 #endif 34 #include <pm_api_sys.h> 35 #include <pm_client.h> 36 37 #include <plat_ocm_coherency.h> 38 39 static entry_point_info_t bl32_image_ep_info; 40 static entry_point_info_t bl33_image_ep_info; 41 42 /* 43 * Return a pointer to the 'entry_point_info' structure of the next image for 44 * the security state specified. BL33 corresponds to the non-secure image type 45 * while BL32 corresponds to the secure image type. A NULL pointer is returned 46 * if the image does not exist. 47 */ 48 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 49 { 50 assert(sec_state_is_valid(type)); 51 52 if (type == NON_SECURE) { 53 return &bl33_image_ep_info; 54 } 55 56 return &bl32_image_ep_info; 57 } 58 59 /* 60 * Set the build time defaults,if we can't find any config data. 61 */ 62 static inline void bl31_set_default_config(void) 63 { 64 bl32_image_ep_info.pc = BL32_BASE; 65 bl32_image_ep_info.spsr = arm_get_spsr(BL32_IMAGE_ID); 66 #if defined(SPD_opteed) 67 #if (TRANSFER_LIST == 0) 68 /* NS dtb addr passed to optee_os */ 69 bl32_image_ep_info.args.arg3 = XILINX_OF_BOARD_DTB_ADDR; 70 #endif 71 #endif 72 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 73 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, 74 DISABLE_ALL_EXCEPTIONS); 75 } 76 77 /* 78 * Perform any BL31 specific platform actions. Here is an opportunity to copy 79 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 80 * are lost (potentially). This needs to be done before the MMU is initialized 81 * so that the memory layout can be used while creating page tables. 82 */ 83 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 84 u_register_t arg2, u_register_t arg3) 85 { 86 (void)arg0; 87 (void)arg1; 88 (void)arg2; 89 (void)arg3; 90 uint32_t uart_clock; 91 #if (TRANSFER_LIST == 1) 92 int32_t rc; 93 bool tl_status = false; 94 #endif 95 96 board_detection(); 97 98 /* FIXME */ 99 switch (platform_id) { 100 case SPP: 101 switch (platform_version) { 102 case SPP_PSXC_MMI_V2_0: 103 cpu_clock = 770000; 104 break; 105 case SPP_PSXC_MMI_V3_0: 106 cpu_clock = 908000; 107 break; 108 default: 109 panic(); 110 } 111 break; 112 case SPP_MMD: 113 switch (platform_version) { 114 case SPP_PSXC_ISP_AIE_V2_0: 115 case SPP_PSXC_MMD_AIE_FRZ_EA: 116 case SPP_PSXC_MMD_AIE_V3_0: 117 cpu_clock = 760000; 118 break; 119 default: 120 panic(); 121 } 122 break; 123 case EMU: 124 case EMU_MMD: 125 cpu_clock = 112203; 126 break; 127 case QEMU: 128 case SILICON: 129 cpu_clock = 100000000; 130 break; 131 default: 132 panic(); 133 } 134 #if (TRANSFER_LIST == 1) 135 tl_status = populate_data_from_xfer_list(); 136 if (tl_status != true) { 137 WARN("Invalid transfer list\n"); 138 } 139 #endif 140 141 uart_clock = get_uart_clk(); 142 143 /* Initialize the platform config for future decision making */ 144 config_setup(); 145 146 setup_console(); 147 148 if (IS_TFA_IN_OCM(BL31_BASE) && (check_ocm_coherency() < 0)) { 149 NOTICE("OCM coherency check not supported\n"); 150 } 151 152 NOTICE("TF-A running on %s v%d.%d, RTL v%d.%d, PS v%d.%d, PMC v%d.%d\n", 153 board_name_decode(), 154 (platform_version >> 1), platform_version % 10U, 155 (rtlversion >> 1), rtlversion % 10U, 156 (psversion >> 1), psversion % 10U, 157 (pmcversion >> 1), pmcversion % 10U); 158 159 /* 160 * Do initial security configuration to allow DRAM/device access. On 161 * Base only DRAM security is programmable (via TrustZone), but 162 * other platforms might have more programmable security devices 163 * present. 164 */ 165 166 /* Populate common information for BL32 and BL33 */ 167 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 168 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 169 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 170 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 171 172 #if (TRANSFER_LIST == 1) 173 rc = transfer_list_populate_ep_info(&bl32_image_ep_info, &bl33_image_ep_info); 174 if (rc == TL_OPS_NON || rc == TL_OPS_CUS) { 175 NOTICE("BL31: TL not found, using default config\n"); 176 bl31_set_default_config(); 177 } 178 #else 179 bl31_set_default_config(); 180 #endif 181 182 long rev_var = cpu_get_rev_var(); 183 184 INFO("CPU Revision = 0x%lx\n", rev_var); 185 INFO("cpu_clock = %dHz, uart_clock = %dHz\n", cpu_clock, uart_clock); 186 NOTICE("BL31: Executing from 0x%x\n", BL31_BASE); 187 #if (defined(SPD_tspd) || defined(SPD_opteed)) 188 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 189 #endif /* SPD_tspd || SPD_opteed */ 190 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 191 192 custom_early_setup(); 193 194 } 195 196 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 197 198 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 199 { 200 static uint32_t index; 201 uint32_t i; 202 int32_t ret = 0; 203 204 /* Validate 'handler' and 'id' parameters */ 205 if ((handler == NULL) || (index >= MAX_INTR_EL3)) { 206 ret = -EINVAL; 207 goto exit_label; 208 } 209 210 /* Check if a handler has already been registered */ 211 for (i = 0; i < index; i++) { 212 if (id == type_el3_interrupt_table[i].id) { 213 ret = -EALREADY; 214 goto exit_label; 215 } 216 } 217 218 type_el3_interrupt_table[index].id = id; 219 type_el3_interrupt_table[index].handler = handler; 220 221 index++; 222 223 exit_label: 224 return ret; 225 } 226 227 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 228 void *handle, void *cookie) 229 { 230 (void)id; 231 uint32_t intr_id; 232 uint32_t i; 233 interrupt_type_handler_t handler = NULL; 234 235 intr_id = plat_ic_get_pending_interrupt_id(); 236 237 for (i = 0; i < MAX_INTR_EL3; i++) { 238 if (intr_id == type_el3_interrupt_table[i].id) { 239 handler = type_el3_interrupt_table[i].handler; 240 } 241 } 242 243 if (handler != NULL) { 244 (void)handler(intr_id, flags, handle, cookie); 245 } 246 247 return 0; 248 } 249 250 void bl31_platform_setup(void) 251 { 252 prepare_dtb(); 253 254 /* Initialize the gic cpu and distributor interfaces */ 255 plat_gic_driver_init(); 256 plat_gic_init(); 257 258 #if (TFA_NO_PM == 1) 259 if (platform_id != EMU) { 260 init_scmi_server(); 261 } 262 #endif 263 } 264 265 void bl31_plat_runtime_setup(void) 266 { 267 uint32_t flags = 0; 268 int32_t rc; 269 uint32_t rre_ret = 0; 270 271 set_interrupt_rm_flag(flags, NON_SECURE); 272 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 273 rdo_el3_interrupt_handler, flags); 274 if (rc != 0) { 275 panic(); 276 } 277 278 /* Instead of calling for each time fill in structure early. */ 279 rre_ret = retrieve_reserved_entries(); 280 281 if (rre_ret != 0) { 282 INFO("Runtime FDT reserve node retreival failed"); 283 } 284 285 custom_runtime_setup(); 286 287 console_switch_state(CONSOLE_FLAG_RUNTIME); 288 } 289 290 /* 291 * Perform the very early platform specific architectural setup here. 292 */ 293 void bl31_plat_arch_setup(void) 294 { 295 const mmap_region_t bl_regions[] = { 296 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 297 MT_MEMORY | MT_RW | MT_SECURE), 298 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 299 MT_CODE | MT_SECURE), 300 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 301 MT_RO_DATA | MT_SECURE), 302 #if (TFA_NO_PM == 1) 303 MAP_REGION_FLAT(SMT_BUFFER_BASE, 0x1000, 304 MT_DEVICE | MT_RW | MT_NON_CACHEABLE | MT_EXECUTE_NEVER | MT_NS), 305 #endif 306 {0} 307 }; 308 309 custom_mmap_add(); 310 311 setup_page_tables(bl_regions, plat_get_mmap()); 312 enable_mmu(0); 313 } 314