1 /* 2 * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/dcc.h> 16 #include <drivers/arm/pl011.h> 17 #include <drivers/console.h> 18 #include <lib/cpus/cpu_ops.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_v2.h> 21 #include <plat/common/platform.h> 22 #include <plat_arm.h> 23 #include <plat_console.h> 24 #include <scmi.h> 25 26 #include <custom_svc.h> 27 #include <def.h> 28 #include <plat_fdt.h> 29 #include <plat_private.h> 30 #include <plat_startup.h> 31 #if TRANSFER_LIST 32 #include <plat_xfer_list.h> 33 #endif 34 #include <pm_api_sys.h> 35 #include <pm_client.h> 36 37 #include <plat_ocm_coherency.h> 38 39 static entry_point_info_t bl32_image_ep_info; 40 static entry_point_info_t bl33_image_ep_info; 41 42 /* 43 * Return a pointer to the 'entry_point_info' structure of the next image for 44 * the security state specified. BL33 corresponds to the non-secure image type 45 * while BL32 corresponds to the secure image type. A NULL pointer is returned 46 * if the image does not exist. 47 */ 48 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 49 { 50 assert(sec_state_is_valid(type)); 51 52 if (type == NON_SECURE) { 53 return &bl33_image_ep_info; 54 } 55 56 return &bl32_image_ep_info; 57 } 58 59 /* 60 * Set the build time defaults,if we can't find any config data. 61 */ 62 static inline void bl31_set_default_config(void) 63 { 64 bl32_image_ep_info.pc = BL32_BASE; 65 bl32_image_ep_info.spsr = arm_get_spsr(BL32_IMAGE_ID); 66 #if defined(SPD_opteed) 67 #if (TRANSFER_LIST == 0) 68 /* NS dtb addr passed to optee_os */ 69 bl32_image_ep_info.args.arg3 = XILINX_OF_BOARD_DTB_ADDR; 70 #endif 71 #endif 72 73 #if defined(SPD_spmd) 74 bl32_image_ep_info.args.arg2 = XILINX_OF_BOARD_DTB_ADDR; 75 bl32_image_ep_info.args.arg0 = SPMC_MANIFEST_DTB_ADDR; 76 #endif 77 78 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 79 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, 80 DISABLE_ALL_EXCEPTIONS); 81 } 82 83 /* 84 * Perform any BL31 specific platform actions. Here is an opportunity to copy 85 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 86 * are lost (potentially). This needs to be done before the MMU is initialized 87 * so that the memory layout can be used while creating page tables. 88 */ 89 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 90 u_register_t arg2, u_register_t arg3) 91 { 92 (void)arg0; 93 (void)arg1; 94 (void)arg2; 95 (void)arg3; 96 uint32_t uart_clock; 97 #if (TRANSFER_LIST == 1) 98 int32_t rc; 99 bool tl_status = false; 100 #endif 101 102 board_detection(); 103 104 /* FIXME */ 105 switch (platform_id) { 106 case SPP: 107 switch (platform_version) { 108 case SPP_PSXC_MMI_V2_0: 109 cpu_clock = 770000; 110 break; 111 case SPP_PSXC_MMI_V3_0: 112 cpu_clock = 908000; 113 break; 114 default: 115 panic(); 116 } 117 break; 118 case SPP_MMD: 119 switch (platform_version) { 120 case SPP_PSXC_ISP_AIE_V2_0: 121 case SPP_PSXC_MMD_AIE_FRZ_EA: 122 case SPP_PSXC_MMD_AIE_V3_0: 123 cpu_clock = 760000; 124 break; 125 default: 126 panic(); 127 } 128 break; 129 case EMU: 130 case EMU_MMD: 131 cpu_clock = 112203; 132 break; 133 case QEMU: 134 case SILICON: 135 cpu_clock = 100000000; 136 break; 137 default: 138 panic(); 139 } 140 #if (TRANSFER_LIST == 1) 141 tl_status = populate_data_from_xfer_list(); 142 if (tl_status != true) { 143 WARN("Invalid transfer list\n"); 144 } 145 #endif 146 147 uart_clock = get_uart_clk(); 148 149 /* Initialize the platform config for future decision making */ 150 config_setup(); 151 152 setup_console(); 153 154 if (IS_TFA_IN_OCM(BL31_BASE) && (check_ocm_coherency() < 0)) { 155 NOTICE("OCM coherency check not supported\n"); 156 } 157 158 NOTICE("TF-A running on %s v%d.%d, RTL v%d.%d, PS v%d.%d, PMC v%d.%d\n", 159 board_name_decode(), 160 (platform_version >> 1), platform_version % 10U, 161 (rtlversion >> 1), rtlversion % 10U, 162 (psversion >> 1), psversion % 10U, 163 (pmcversion >> 1), pmcversion % 10U); 164 165 /* 166 * Do initial security configuration to allow DRAM/device access. On 167 * Base only DRAM security is programmable (via TrustZone), but 168 * other platforms might have more programmable security devices 169 * present. 170 */ 171 172 /* Populate common information for BL32 and BL33 */ 173 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 174 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 175 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 176 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 177 178 #if (TRANSFER_LIST == 1) 179 rc = transfer_list_populate_ep_info(&bl32_image_ep_info, &bl33_image_ep_info); 180 if (rc == TL_OPS_NON || rc == TL_OPS_CUS) { 181 NOTICE("BL31: TL not found, using default config\n"); 182 bl31_set_default_config(); 183 } 184 #else 185 bl31_set_default_config(); 186 #endif 187 188 long rev_var = cpu_get_rev_var(); 189 190 INFO("CPU Revision = 0x%lx\n", rev_var); 191 INFO("cpu_clock = %dHz, uart_clock = %dHz\n", cpu_clock, uart_clock); 192 NOTICE("BL31: Executing from 0x%x\n", BL31_BASE); 193 #if (defined(SPD_tspd) || defined(SPD_opteed)) 194 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 195 #endif /* SPD_tspd || SPD_opteed */ 196 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 197 198 custom_early_setup(); 199 200 } 201 202 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 203 204 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 205 { 206 static uint32_t index; 207 uint32_t i; 208 int32_t ret = 0; 209 210 /* Validate 'handler' and 'id' parameters */ 211 if ((handler == NULL) || (index >= MAX_INTR_EL3)) { 212 ret = -EINVAL; 213 goto exit_label; 214 } 215 216 /* Check if a handler has already been registered */ 217 for (i = 0; i < index; i++) { 218 if (id == type_el3_interrupt_table[i].id) { 219 ret = -EALREADY; 220 goto exit_label; 221 } 222 } 223 224 type_el3_interrupt_table[index].id = id; 225 type_el3_interrupt_table[index].handler = handler; 226 227 index++; 228 229 exit_label: 230 return ret; 231 } 232 233 #if defined(SPD_none) || defined(SPD_opteed) 234 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 235 void *handle, void *cookie) 236 { 237 (void)id; 238 uint32_t intr_id; 239 uint32_t i; 240 interrupt_type_handler_t handler = NULL; 241 242 intr_id = plat_ic_get_pending_interrupt_id(); 243 244 for (i = 0; i < MAX_INTR_EL3; i++) { 245 if (intr_id == type_el3_interrupt_table[i].id) { 246 handler = type_el3_interrupt_table[i].handler; 247 } 248 } 249 250 if (handler != NULL) { 251 (void)handler(intr_id, flags, handle, cookie); 252 } 253 254 return 0; 255 } 256 #endif 257 258 #if defined(SPD_spmd) 259 int plat_spmd_handle_group0_interrupt(uint32_t intid) 260 { 261 uint32_t i; 262 interrupt_type_handler_t handler = NULL; 263 264 for (i = 0; i < MAX_INTR_EL3; i++) { 265 if (intid == type_el3_interrupt_table[i].id) { 266 handler = type_el3_interrupt_table[i].handler; 267 } 268 } 269 270 if (handler != NULL) { 271 /* TODO: Review handler logic and add error handling if needed */ 272 (void)handler(intid, 0, NULL, NULL); 273 } 274 275 return 0; 276 } 277 #endif 278 279 void bl31_platform_setup(void) 280 { 281 prepare_dtb(); 282 283 /* Initialize the gic cpu and distributor interfaces */ 284 plat_gic_driver_init(); 285 plat_gic_init(); 286 287 #if (TFA_NO_PM == 1) 288 if (platform_id != EMU) { 289 init_scmi_server(); 290 } 291 #endif 292 } 293 294 void bl31_plat_runtime_setup(void) 295 { 296 uint32_t rre_ret = 0; 297 #if defined(SPD_none) || defined(SPD_opteed) 298 uint32_t flags = 0; 299 int32_t rc; 300 301 set_interrupt_rm_flag(flags, NON_SECURE); 302 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 303 rdo_el3_interrupt_handler, flags); 304 if (rc != 0) { 305 panic(); 306 } 307 #endif 308 309 /* Instead of calling for each time fill in structure early. */ 310 rre_ret = retrieve_reserved_entries(); 311 312 if (rre_ret != 0) { 313 INFO("Runtime FDT reserve node retreival failed"); 314 } 315 316 custom_runtime_setup(); 317 318 console_switch_state(CONSOLE_FLAG_RUNTIME); 319 } 320 321 /* 322 * Perform the very early platform specific architectural setup here. 323 */ 324 void bl31_plat_arch_setup(void) 325 { 326 const mmap_region_t bl_regions[] = { 327 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 328 MT_MEMORY | MT_RW | MT_SECURE), 329 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 330 MT_CODE | MT_SECURE), 331 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 332 MT_RO_DATA | MT_SECURE), 333 #if (TFA_NO_PM == 1) 334 MAP_REGION_FLAT(SMT_BUFFER_BASE, 0x1000, 335 MT_DEVICE | MT_RW | MT_NON_CACHEABLE | MT_EXECUTE_NEVER | MT_NS), 336 #endif 337 {0} 338 }; 339 340 custom_mmap_add(); 341 342 setup_page_tables(bl_regions, plat_get_mmap()); 343 enable_mmu(0); 344 } 345