1*c97857dbSAmit Nagal/* 2*c97857dbSAmit Nagal * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 3*c97857dbSAmit Nagal * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4*c97857dbSAmit Nagal * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5*c97857dbSAmit Nagal * 6*c97857dbSAmit Nagal * SPDX-License-Identifier: BSD-3-Clause 7*c97857dbSAmit Nagal */ 8*c97857dbSAmit Nagal 9*c97857dbSAmit Nagal#include <arch.h> 10*c97857dbSAmit Nagal#include <asm_macros.S> 11*c97857dbSAmit Nagal#include <drivers/arm/gicv3.h> 12*c97857dbSAmit Nagal 13*c97857dbSAmit Nagal#include <platform_def.h> 14*c97857dbSAmit Nagal 15*c97857dbSAmit Nagal .globl plat_secondary_cold_boot_setup 16*c97857dbSAmit Nagal .globl plat_is_my_cpu_primary 17*c97857dbSAmit Nagal .globl platform_mem_init 18*c97857dbSAmit Nagal .globl plat_my_core_pos 19*c97857dbSAmit Nagal 20*c97857dbSAmit Nagal /* ----------------------------------------------------- 21*c97857dbSAmit Nagal * void plat_secondary_cold_boot_setup (void); 22*c97857dbSAmit Nagal * 23*c97857dbSAmit Nagal * This function performs any platform specific actions 24*c97857dbSAmit Nagal * needed for a secondary cpu after a cold reset e.g 25*c97857dbSAmit Nagal * mark the cpu's presence, mechanism to place it in a 26*c97857dbSAmit Nagal * holding pen etc. 27*c97857dbSAmit Nagal * TODO: Should we read the PSYS register to make sure 28*c97857dbSAmit Nagal * that the request has gone through. 29*c97857dbSAmit Nagal * ----------------------------------------------------- 30*c97857dbSAmit Nagal */ 31*c97857dbSAmit Nagalfunc plat_secondary_cold_boot_setup 32*c97857dbSAmit Nagal mrs x0, mpidr_el1 33*c97857dbSAmit Nagal 34*c97857dbSAmit Nagal /* 35*c97857dbSAmit Nagal * There is no sane reason to come out of this wfi. This 36*c97857dbSAmit Nagal * cpu will be powered on and reset by the cpu_on pm api 37*c97857dbSAmit Nagal */ 38*c97857dbSAmit Nagal dsb sy 39*c97857dbSAmit Nagal bl plat_panic_handler 40*c97857dbSAmit Nagalendfunc plat_secondary_cold_boot_setup 41*c97857dbSAmit Nagal 42*c97857dbSAmit Nagalfunc plat_is_my_cpu_primary 43*c97857dbSAmit Nagal mov x9, x30 44*c97857dbSAmit Nagal bl plat_my_core_pos 45*c97857dbSAmit Nagal cmp x0, #PRIMARY_CPU 46*c97857dbSAmit Nagal cset x0, eq 47*c97857dbSAmit Nagal ret x9 48*c97857dbSAmit Nagalendfunc plat_is_my_cpu_primary 49*c97857dbSAmit Nagal 50*c97857dbSAmit Nagal /* ----------------------------------------------------- 51*c97857dbSAmit Nagal * unsigned int plat_my_core_pos(void) 52*c97857dbSAmit Nagal * This function uses the plat_core_pos_by_mpidr() 53*c97857dbSAmit Nagal * definition to get the index of the calling CPU. 54*c97857dbSAmit Nagal * ----------------------------------------------------- 55*c97857dbSAmit Nagal */ 56*c97857dbSAmit Nagalfunc plat_my_core_pos 57*c97857dbSAmit Nagal mrs x0, mpidr_el1 58*c97857dbSAmit Nagal b plat_core_pos_by_mpidr 59*c97857dbSAmit Nagalendfunc plat_my_core_pos 60*c97857dbSAmit Nagal 61*c97857dbSAmit Nagal /* --------------------------------------------------------------------- 62*c97857dbSAmit Nagal * We don't need to carry out any memory initialization on platform 63*c97857dbSAmit Nagal * The Secure RAM is accessible straight away. 64*c97857dbSAmit Nagal * --------------------------------------------------------------------- 65*c97857dbSAmit Nagal */ 66*c97857dbSAmit Nagalfunc platform_mem_init 67*c97857dbSAmit Nagal ret 68*c97857dbSAmit Nagalendfunc platform_mem_init 69