1*13bacd3bSIcenowy Zheng /* 2*13bacd3bSIcenowy Zheng * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3*13bacd3bSIcenowy Zheng * 4*13bacd3bSIcenowy Zheng * SPDX-License-Identifier: BSD-3-Clause 5*13bacd3bSIcenowy Zheng */ 6*13bacd3bSIcenowy Zheng 7*13bacd3bSIcenowy Zheng #ifndef SUNXI_MMAP_H 8*13bacd3bSIcenowy Zheng #define SUNXI_MMAP_H 9*13bacd3bSIcenowy Zheng 10*13bacd3bSIcenowy Zheng /* Memory regions */ 11*13bacd3bSIcenowy Zheng #define SUNXI_ROM_BASE 0x00000000 12*13bacd3bSIcenowy Zheng #define SUNXI_ROM_SIZE 0x00010000 13*13bacd3bSIcenowy Zheng /* 14*13bacd3bSIcenowy Zheng * In fact all SRAM from 0x100000 is SRAM A2. However as it's too big for 15*13bacd3bSIcenowy Zheng * firmware, and the user manual gives a tip on a 2*64K/27*64K partition, 16*13bacd3bSIcenowy Zheng * only use the first 2*64K for firmwares now, with the SPL using the first 17*13bacd3bSIcenowy Zheng * 64K and BL3-1 using the second one. 18*13bacd3bSIcenowy Zheng * 19*13bacd3bSIcenowy Zheng * Only the used 2*64K SRAM is defined here, to prevent a gaint translation 20*13bacd3bSIcenowy Zheng * table to be generated. 21*13bacd3bSIcenowy Zheng */ 22*13bacd3bSIcenowy Zheng #define SUNXI_SRAM_BASE 0x00100000 23*13bacd3bSIcenowy Zheng #define SUNXI_SRAM_SIZE 0x00020000 24*13bacd3bSIcenowy Zheng #define SUNXI_SRAM_A1_BASE 0x00100000 25*13bacd3bSIcenowy Zheng #define SUNXI_SRAM_A1_SIZE 0x00010000 26*13bacd3bSIcenowy Zheng #define SUNXI_SRAM_A2_BASE 0x00110000 27*13bacd3bSIcenowy Zheng #define SUNXI_SRAM_A2_BL31_OFFSET 0x00000000 28*13bacd3bSIcenowy Zheng #define SUNXI_SRAM_A2_SIZE 0x00010000 29*13bacd3bSIcenowy Zheng #define SUNXI_DEV_BASE 0x01000000 30*13bacd3bSIcenowy Zheng #define SUNXI_DEV_SIZE 0x09000000 31*13bacd3bSIcenowy Zheng #define SUNXI_DRAM_BASE 0x40000000 32*13bacd3bSIcenowy Zheng #define SUNXI_DRAM_VIRT_BASE 0x0a000000 33*13bacd3bSIcenowy Zheng 34*13bacd3bSIcenowy Zheng /* Memory-mapped devices */ 35*13bacd3bSIcenowy Zheng #define SUNXI_WDOG_BASE 0x020000a0 36*13bacd3bSIcenowy Zheng #define SUNXI_R_WDOG_BASE SUNXI_WDOG_BASE 37*13bacd3bSIcenowy Zheng #define SUNXI_PIO_BASE 0x02000400 38*13bacd3bSIcenowy Zheng #define SUNXI_SPC_BASE 0x02000800 39*13bacd3bSIcenowy Zheng #define SUNXI_CCU_BASE 0x02001000 40*13bacd3bSIcenowy Zheng #define SUNXI_UART0_BASE 0x02500000 41*13bacd3bSIcenowy Zheng #define SUNXI_SYSCON_BASE 0x03000000 42*13bacd3bSIcenowy Zheng #define SUNXI_DMA_BASE 0x03002000 43*13bacd3bSIcenowy Zheng #define SUNXI_SID_BASE 0x03006000 44*13bacd3bSIcenowy Zheng #define SUNXI_GICD_BASE 0x03021000 45*13bacd3bSIcenowy Zheng #define SUNXI_GICC_BASE 0x03022000 46*13bacd3bSIcenowy Zheng #define SUNXI_SPI0_BASE 0x04025000 47*13bacd3bSIcenowy Zheng #define SUNXI_R_CPUCFG_BASE 0x07000400 48*13bacd3bSIcenowy Zheng #define SUNXI_R_PRCM_BASE 0x07010000 49*13bacd3bSIcenowy Zheng #define SUNXI_R_PIO_BASE 0x07022000 50*13bacd3bSIcenowy Zheng #define SUNXI_R_UART_BASE 0x07080000 51*13bacd3bSIcenowy Zheng #define SUNXI_R_I2C_BASE 0x07081400 52*13bacd3bSIcenowy Zheng #define SUNXI_CPUCFG_BASE 0x08100000 53*13bacd3bSIcenowy Zheng #define SUNXI_C0_CPUXCFG_BASE 0x09010000 54*13bacd3bSIcenowy Zheng 55*13bacd3bSIcenowy Zheng #endif /* SUNXI_MMAP_H */ 56