1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io> 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <errno.h> 9 10 #include <libfdt.h> 11 12 #include <platform_def.h> 13 14 #include <arch_helpers.h> 15 #include <common/debug.h> 16 #include <drivers/allwinner/sunxi_rsb.h> 17 #include <drivers/delay_timer.h> 18 #include <lib/mmio.h> 19 20 #include <sunxi_def.h> 21 #include <sunxi_mmap.h> 22 #include <sunxi_private.h> 23 24 static enum pmic_type { 25 GENERIC_H5, 26 GENERIC_A64, 27 REF_DESIGN_H5, /* regulators controlled by GPIO pins on port L */ 28 AXP803_RSB, /* PMIC connected via RSB on most A64 boards */ 29 } pmic; 30 31 #define AXP803_HW_ADDR 0x3a3 32 #define AXP803_RT_ADDR 0x2d 33 34 /* 35 * On boards without a proper PMIC we struggle to turn off the system properly. 36 * Try to turn off as much off the system as we can, to reduce power 37 * consumption. This should be entered with only one core running and SMP 38 * disabled. 39 * This function only cares about peripherals. 40 */ 41 void sunxi_turn_off_soc(uint16_t socid) 42 { 43 int i; 44 45 /** Turn off most peripherals, most importantly DRAM users. **/ 46 /* Keep DRAM controller running for now. */ 47 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, ~BIT_32(14)); 48 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, ~BIT_32(14)); 49 /* Contains msgbox (bit 21) and spinlock (bit 22) */ 50 mmio_write_32(SUNXI_CCU_BASE + 0x2c4, 0); 51 mmio_write_32(SUNXI_CCU_BASE + 0x64, 0); 52 mmio_write_32(SUNXI_CCU_BASE + 0x2c8, 0); 53 /* Keep PIO controller running for now. */ 54 mmio_clrbits_32(SUNXI_CCU_BASE + 0x68, ~(BIT_32(5))); 55 mmio_write_32(SUNXI_CCU_BASE + 0x2d0, 0); 56 /* Contains UART0 (bit 16) */ 57 mmio_write_32(SUNXI_CCU_BASE + 0x2d8, 0); 58 mmio_write_32(SUNXI_CCU_BASE + 0x6c, 0); 59 mmio_write_32(SUNXI_CCU_BASE + 0x70, 0); 60 61 /** Turn off DRAM controller. **/ 62 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, BIT_32(14)); 63 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, BIT_32(14)); 64 65 /** Migrate CPU and bus clocks away from the PLLs. **/ 66 /* AHB1: use OSC24M/1, APB1 = AHB1 / 2 */ 67 mmio_write_32(SUNXI_CCU_BASE + 0x54, 0x1000); 68 /* APB2: use OSC24M */ 69 mmio_write_32(SUNXI_CCU_BASE + 0x58, 0x1000000); 70 /* AHB2: use AHB1 clock */ 71 mmio_write_32(SUNXI_CCU_BASE + 0x5c, 0); 72 /* CPU: use OSC24M */ 73 mmio_write_32(SUNXI_CCU_BASE + 0x50, 0x10000); 74 75 /** Turn off PLLs. **/ 76 for (i = 0; i < 6; i++) 77 mmio_clrbits_32(SUNXI_CCU_BASE + i * 8, BIT(31)); 78 switch (socid) { 79 case SUNXI_SOC_H5: 80 mmio_clrbits_32(SUNXI_CCU_BASE + 0x44, BIT(31)); 81 break; 82 case SUNXI_SOC_A64: 83 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c, BIT(31)); 84 mmio_clrbits_32(SUNXI_CCU_BASE + 0x4c, BIT(31)); 85 break; 86 } 87 } 88 89 static int rsb_init(void) 90 { 91 int ret; 92 93 ret = rsb_init_controller(); 94 if (ret) 95 return ret; 96 97 /* Start with 400 KHz to issue the I2C->RSB switch command. */ 98 ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 400000); 99 if (ret) 100 return ret; 101 102 /* 103 * Initiate an I2C transaction to write 0x7c into register 0x3e, 104 * switching the PMIC to RSB mode. 105 */ 106 ret = rsb_set_device_mode(0x7c3e00); 107 if (ret) 108 return ret; 109 110 /* Now in RSB mode, switch to the recommended 3 MHz. */ 111 ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000); 112 if (ret) 113 return ret; 114 115 /* Associate the 8-bit runtime address with the 12-bit bus address. */ 116 return rsb_assign_runtime_address(AXP803_HW_ADDR, 117 AXP803_RT_ADDR); 118 } 119 120 static int axp_write(uint8_t reg, uint8_t val) 121 { 122 return rsb_write(AXP803_RT_ADDR, reg, val); 123 } 124 125 static int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask) 126 { 127 uint8_t regval; 128 int ret; 129 130 ret = rsb_read(AXP803_RT_ADDR, reg); 131 if (ret < 0) 132 return ret; 133 134 regval = (ret & ~clr_mask) | set_mask; 135 136 return rsb_write(AXP803_RT_ADDR, reg, regval); 137 } 138 139 #define axp_clrbits(reg, clr_mask) axp_clrsetbits(reg, clr_mask, 0) 140 #define axp_setbits(reg, set_mask) axp_clrsetbits(reg, 0, set_mask) 141 142 static bool should_enable_regulator(const void *fdt, int node) 143 { 144 if (fdt_getprop(fdt, node, "phandle", NULL) != NULL) 145 return true; 146 if (fdt_getprop(fdt, node, "regulator-always-on", NULL) != NULL) 147 return true; 148 return false; 149 } 150 151 /* 152 * Retrieve the voltage from a given regulator DTB node. 153 * Both the regulator-{min,max}-microvolt properties must be present and 154 * have the same value. Return that value in millivolts. 155 */ 156 static int fdt_get_regulator_millivolt(const void *fdt, int node) 157 { 158 const fdt32_t *prop; 159 uint32_t min_volt; 160 161 prop = fdt_getprop(fdt, node, "regulator-min-microvolt", NULL); 162 if (prop == NULL) 163 return -EINVAL; 164 min_volt = fdt32_to_cpu(*prop); 165 166 prop = fdt_getprop(fdt, node, "regulator-max-microvolt", NULL); 167 if (prop == NULL) 168 return -EINVAL; 169 170 if (fdt32_to_cpu(*prop) != min_volt) 171 return -EINVAL; 172 173 return min_volt / 1000; 174 } 175 176 #define NO_SPLIT 0xff 177 178 static const struct axp_regulator { 179 char *dt_name; 180 uint16_t min_volt; 181 uint16_t max_volt; 182 uint16_t step; 183 unsigned char split; 184 unsigned char volt_reg; 185 unsigned char switch_reg; 186 unsigned char switch_bit; 187 } regulators[] = { 188 {"dcdc1", 1600, 3400, 100, NO_SPLIT, 0x20, 0x10, 0}, 189 {"dcdc5", 800, 1840, 10, 32, 0x24, 0x10, 4}, 190 {"dcdc6", 600, 1520, 10, 50, 0x25, 0x10, 5}, 191 {"dldo1", 700, 3300, 100, NO_SPLIT, 0x15, 0x12, 3}, 192 {"dldo2", 700, 4200, 100, 27, 0x16, 0x12, 4}, 193 {"dldo3", 700, 3300, 100, NO_SPLIT, 0x17, 0x12, 5}, 194 {"fldo1", 700, 1450, 50, NO_SPLIT, 0x1c, 0x13, 2}, 195 {} 196 }; 197 198 static int setup_regulator(const void *fdt, int node, 199 const struct axp_regulator *reg) 200 { 201 int mvolt; 202 uint8_t regval; 203 204 if (!should_enable_regulator(fdt, node)) 205 return -ENOENT; 206 207 mvolt = fdt_get_regulator_millivolt(fdt, node); 208 if (mvolt < reg->min_volt || mvolt > reg->max_volt) 209 return -EINVAL; 210 211 regval = (mvolt / reg->step) - (reg->min_volt / reg->step); 212 if (regval > reg->split) 213 regval = ((regval - reg->split) / 2) + reg->split; 214 215 axp_write(reg->volt_reg, regval); 216 if (reg->switch_reg < 0xff) 217 axp_setbits(reg->switch_reg, BIT(reg->switch_bit)); 218 219 INFO("PMIC: AXP803: %s voltage: %d.%03dV\n", reg->dt_name, 220 mvolt / 1000, mvolt % 1000); 221 222 return 0; 223 } 224 225 static void setup_axp803_rails(const void *fdt) 226 { 227 int node; 228 bool dc1sw = false; 229 230 /* locate the PMIC DT node, bail out if not found */ 231 node = fdt_node_offset_by_compatible(fdt, -1, "x-powers,axp803"); 232 if (node < 0) { 233 WARN("BL31: PMIC: Cannot find AXP803 DT node, skipping initial setup.\n"); 234 return; 235 } 236 237 if (fdt_getprop(fdt, node, "x-powers,drive-vbus-en", NULL)) { 238 axp_clrbits(0x8f, BIT(4)); 239 axp_setbits(0x30, BIT(2)); 240 INFO("PMIC: AXP803: Enabling DRIVEVBUS\n"); 241 } 242 243 /* descend into the "regulators" subnode */ 244 node = fdt_subnode_offset(fdt, node, "regulators"); 245 if (node < 0) { 246 WARN("BL31: PMIC: Cannot find regulators subnode, skipping initial setup.\n"); 247 return; 248 } 249 250 /* iterate over all regulators to find used ones */ 251 for (node = fdt_first_subnode(fdt, node); 252 node >= 0; 253 node = fdt_next_subnode(fdt, node)) { 254 const struct axp_regulator *reg; 255 const char *name; 256 int length; 257 258 /* We only care if it's always on or referenced. */ 259 if (!should_enable_regulator(fdt, node)) 260 continue; 261 262 name = fdt_get_name(fdt, node, &length); 263 for (reg = regulators; reg->dt_name; reg++) { 264 if (!strncmp(name, reg->dt_name, length)) { 265 setup_regulator(fdt, node, reg); 266 break; 267 } 268 } 269 270 if (!strncmp(name, "dc1sw", length)) { 271 /* Delay DC1SW enablement to avoid overheating. */ 272 dc1sw = true; 273 continue; 274 } 275 } 276 /* 277 * If DLDO2 is enabled after DC1SW, the PMIC overheats and shuts 278 * down. So always enable DC1SW as the very last regulator. 279 */ 280 if (dc1sw) { 281 INFO("PMIC: AXP803: Enabling DC1SW\n"); 282 axp_setbits(0x12, BIT(7)); 283 } 284 } 285 286 int sunxi_pmic_setup(uint16_t socid, const void *fdt) 287 { 288 int ret; 289 290 switch (socid) { 291 case SUNXI_SOC_H5: 292 pmic = REF_DESIGN_H5; 293 NOTICE("BL31: PMIC: Defaulting to PortL GPIO according to H5 reference design.\n"); 294 break; 295 case SUNXI_SOC_A64: 296 pmic = GENERIC_A64; 297 ret = sunxi_init_platform_r_twi(socid, true); 298 if (ret) 299 return ret; 300 301 ret = rsb_init(); 302 if (ret) 303 return ret; 304 305 pmic = AXP803_RSB; 306 NOTICE("BL31: PMIC: Detected AXP803 on RSB.\n"); 307 308 if (fdt) 309 setup_axp803_rails(fdt); 310 311 break; 312 default: 313 NOTICE("BL31: PMIC: No support for Allwinner %x SoC.\n", socid); 314 return -ENODEV; 315 } 316 return 0; 317 } 318 319 void __dead2 sunxi_power_down(void) 320 { 321 switch (pmic) { 322 case GENERIC_H5: 323 /* Turn off as many peripherals and clocks as we can. */ 324 sunxi_turn_off_soc(SUNXI_SOC_H5); 325 /* Turn off the pin controller now. */ 326 mmio_write_32(SUNXI_CCU_BASE + 0x68, 0); 327 break; 328 case GENERIC_A64: 329 /* Turn off as many peripherals and clocks as we can. */ 330 sunxi_turn_off_soc(SUNXI_SOC_A64); 331 /* Turn off the pin controller now. */ 332 mmio_write_32(SUNXI_CCU_BASE + 0x68, 0); 333 break; 334 case REF_DESIGN_H5: 335 sunxi_turn_off_soc(SUNXI_SOC_H5); 336 337 /* 338 * Switch PL pins to power off the board: 339 * - PL5 (VCC_IO) -> high 340 * - PL8 (PWR-STB = CPU power supply) -> low 341 * - PL9 (PWR-DRAM) ->low 342 * - PL10 (power LED) -> low 343 * Note: Clearing PL8 will reset the board, so keep it up. 344 */ 345 sunxi_set_gpio_out('L', 5, 1); 346 sunxi_set_gpio_out('L', 9, 0); 347 sunxi_set_gpio_out('L', 10, 0); 348 349 /* Turn off pin controller now. */ 350 mmio_write_32(SUNXI_CCU_BASE + 0x68, 0); 351 352 break; 353 case AXP803_RSB: 354 /* (Re-)init RSB in case the rich OS has disabled it. */ 355 sunxi_init_platform_r_twi(SUNXI_SOC_A64, true); 356 rsb_init(); 357 358 /* Set "power disable control" bit */ 359 axp_setbits(0x32, BIT(7)); 360 break; 361 default: 362 break; 363 } 364 365 udelay(1000); 366 ERROR("PSCI: Cannot turn off system, halting.\n"); 367 wfi(); 368 panic(); 369 } 370