1*333d66cfSSamuel Holland /* 2*333d66cfSSamuel Holland * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3*333d66cfSSamuel Holland * 4*333d66cfSSamuel Holland * SPDX-License-Identifier: BSD-3-Clause 5*333d66cfSSamuel Holland */ 6*333d66cfSSamuel Holland 7*333d66cfSSamuel Holland #ifndef __SUNXI_CPUCFG_H__ 8*333d66cfSSamuel Holland #define __SUNXI_CPUCFG_H__ 9*333d66cfSSamuel Holland 10*333d66cfSSamuel Holland #include <sunxi_mmap.h> 11*333d66cfSSamuel Holland 12*333d66cfSSamuel Holland /* c = cluster, n = core */ 13*333d66cfSSamuel Holland #define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0000 + (c) * 16) 14*333d66cfSSamuel Holland #define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_CPUCFG_BASE + 0x0004 + (c) * 16) 15*333d66cfSSamuel Holland #define SUNXI_CPUCFG_CACHE_CFG_REG0 (SUNXI_CPUCFG_BASE + 0x0008) 16*333d66cfSSamuel Holland #define SUNXI_CPUCFG_CACHE_CFG_REG1 (SUNXI_CPUCFG_BASE + 0x000c) 17*333d66cfSSamuel Holland #define SUNXI_CPUCFG_DBG_REG0 (SUNXI_CPUCFG_BASE + 0x0020) 18*333d66cfSSamuel Holland #define SUNXI_CPUCFG_GLB_CTRL_REG (SUNXI_CPUCFG_BASE + 0x0028) 19*333d66cfSSamuel Holland #define SUNXI_CPUCFG_CPU_STS_REG(c) (SUNXI_CPUCFG_BASE + 0x0030 + (c) * 4) 20*333d66cfSSamuel Holland #define SUNXI_CPUCFG_L2_STS_REG (SUNXI_CPUCFG_BASE + 0x003c) 21*333d66cfSSamuel Holland #define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_CPUCFG_BASE + 0x0080 + (c) * 4) 22*333d66cfSSamuel Holland #define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x00a0 + (n) * 8) 23*333d66cfSSamuel Holland #define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x00a4 + (n) * 8) 24*333d66cfSSamuel Holland 25*333d66cfSSamuel Holland #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_PRCM_BASE + 0x0140 + \ 26*333d66cfSSamuel Holland (c) * 16 + (n) * 4) 27*333d66cfSSamuel Holland #define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_PRCM_BASE + 0x0100 + (c) * 4) 28*333d66cfSSamuel Holland #define SUNXI_R_CPUCFG_CPUS_RST_REG (SUNXI_R_CPUCFG_BASE + 0x0000) 29*333d66cfSSamuel Holland #define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0030 + (c) * 4) 30*333d66cfSSamuel Holland #define SUNXI_R_CPUCFG_SYS_RST_REG (SUNXI_R_CPUCFG_BASE + 0x0140) 31*333d66cfSSamuel Holland #define SUNXI_R_CPUCFG_SS_FLAG_REG (SUNXI_R_CPUCFG_BASE + 0x01a0) 32*333d66cfSSamuel Holland #define SUNXI_R_CPUCFG_CPU_ENTRY_REG (SUNXI_R_CPUCFG_BASE + 0x01a4) 33*333d66cfSSamuel Holland #define SUNXI_R_CPUCFG_SS_ENTRY_REG (SUNXI_R_CPUCFG_BASE + 0x01a8) 34*333d66cfSSamuel Holland #define SUNXI_R_CPUCFG_HP_FLAG_REG (SUNXI_R_CPUCFG_BASE + 0x01ac) 35*333d66cfSSamuel Holland 36*333d66cfSSamuel Holland #endif /* __SUNXI_CPUCFG_H__ */ 37