1*58032586SSamuel Holland /* 2*58032586SSamuel Holland * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3*58032586SSamuel Holland * 4*58032586SSamuel Holland * SPDX-License-Identifier: BSD-3-Clause 5*58032586SSamuel Holland */ 6*58032586SSamuel Holland 7*58032586SSamuel Holland #include <arch.h> 8*58032586SSamuel Holland #include <platform.h> 9*58032586SSamuel Holland #include <platform_def.h> 10*58032586SSamuel Holland 11*58032586SSamuel Holland static unsigned char plat_power_domain_tree_desc[PLAT_MAX_PWR_LVL + 1] = { 12*58032586SSamuel Holland /* One root node for the SoC */ 13*58032586SSamuel Holland 1, 14*58032586SSamuel Holland /* One node for each cluster */ 15*58032586SSamuel Holland PLATFORM_CLUSTER_COUNT, 16*58032586SSamuel Holland /* One set of CPUs per cluster */ 17*58032586SSamuel Holland PLATFORM_MAX_CPUS_PER_CLUSTER, 18*58032586SSamuel Holland }; 19*58032586SSamuel Holland 20*58032586SSamuel Holland int plat_core_pos_by_mpidr(u_register_t mpidr) 21*58032586SSamuel Holland { 22*58032586SSamuel Holland unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); 23*58032586SSamuel Holland unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); 24*58032586SSamuel Holland 25*58032586SSamuel Holland if (MPIDR_AFFLVL3_VAL(mpidr) > 0 || 26*58032586SSamuel Holland MPIDR_AFFLVL2_VAL(mpidr) > 0 || 27*58032586SSamuel Holland cluster >= PLATFORM_CLUSTER_COUNT || 28*58032586SSamuel Holland core >= PLATFORM_MAX_CPUS_PER_CLUSTER) { 29*58032586SSamuel Holland return -1; 30*58032586SSamuel Holland } 31*58032586SSamuel Holland 32*58032586SSamuel Holland return cluster * PLATFORM_MAX_CPUS_PER_CLUSTER + core; 33*58032586SSamuel Holland } 34*58032586SSamuel Holland 35*58032586SSamuel Holland const unsigned char *plat_get_power_domain_tree_desc(void) 36*58032586SSamuel Holland { 37*58032586SSamuel Holland return plat_power_domain_tree_desc; 38*58032586SSamuel Holland } 39