1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <debug.h> 10 #include <delay_timer.h> 11 #include <gicv2.h> 12 #include <mmio.h> 13 #include <platform.h> 14 #include <platform_def.h> 15 #include <psci.h> 16 #include <sunxi_cpucfg.h> 17 #include <sunxi_mmap.h> 18 #include <sunxi_private.h> 19 20 #define SUNXI_WDOG0_CTRL_REG (SUNXI_WDOG_BASE + 0x0010) 21 #define SUNXI_WDOG0_CFG_REG (SUNXI_WDOG_BASE + 0x0014) 22 #define SUNXI_WDOG0_MODE_REG (SUNXI_WDOG_BASE + 0x0018) 23 24 #define mpidr_is_valid(mpidr) ( \ 25 MPIDR_AFFLVL3_VAL(mpidr) == 0 && \ 26 MPIDR_AFFLVL2_VAL(mpidr) == 0 && \ 27 MPIDR_AFFLVL1_VAL(mpidr) < PLATFORM_CLUSTER_COUNT && \ 28 MPIDR_AFFLVL0_VAL(mpidr) < PLATFORM_MAX_CPUS_PER_CLUSTER) 29 30 static int sunxi_pwr_domain_on(u_register_t mpidr) 31 { 32 if (mpidr_is_valid(mpidr) == 0) 33 return PSCI_E_INTERN_FAIL; 34 35 sunxi_cpu_on(MPIDR_AFFLVL1_VAL(mpidr), MPIDR_AFFLVL0_VAL(mpidr)); 36 37 return PSCI_E_SUCCESS; 38 } 39 40 static void sunxi_pwr_domain_off(const psci_power_state_t *target_state) 41 { 42 gicv2_cpuif_disable(); 43 } 44 45 static void __dead2 sunxi_pwr_down_wfi(const psci_power_state_t *target_state) 46 { 47 u_register_t mpidr = read_mpidr(); 48 49 sunxi_cpu_off(MPIDR_AFFLVL1_VAL(mpidr), MPIDR_AFFLVL0_VAL(mpidr)); 50 51 while (1) 52 wfi(); 53 } 54 55 static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state) 56 { 57 gicv2_pcpu_distif_init(); 58 gicv2_cpuif_enable(); 59 } 60 61 static void __dead2 sunxi_system_off(void) 62 { 63 /* Turn off all secondary CPUs */ 64 sunxi_disable_secondary_cpus(plat_my_core_pos()); 65 66 sunxi_power_down(); 67 } 68 69 static void __dead2 sunxi_system_reset(void) 70 { 71 /* Reset the whole system when the watchdog times out */ 72 mmio_write_32(SUNXI_WDOG0_CFG_REG, 1); 73 /* Enable the watchdog with the shortest timeout (0.5 seconds) */ 74 mmio_write_32(SUNXI_WDOG0_MODE_REG, (0 << 4) | 1); 75 /* Wait for twice the watchdog timeout before panicking */ 76 mdelay(1000); 77 78 ERROR("PSCI: System reset failed\n"); 79 wfi(); 80 panic(); 81 } 82 83 static int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint) 84 { 85 /* The non-secure entry point must be in DRAM */ 86 if (ns_entrypoint >= SUNXI_DRAM_BASE) 87 return PSCI_E_SUCCESS; 88 89 return PSCI_E_INVALID_ADDRESS; 90 } 91 92 static plat_psci_ops_t sunxi_psci_ops = { 93 .pwr_domain_on = sunxi_pwr_domain_on, 94 .pwr_domain_off = sunxi_pwr_domain_off, 95 .pwr_domain_pwr_down_wfi = sunxi_pwr_down_wfi, 96 .pwr_domain_on_finish = sunxi_pwr_domain_on_finish, 97 .system_off = sunxi_system_off, 98 .system_reset = sunxi_system_reset, 99 .validate_ns_entrypoint = sunxi_validate_ns_entrypoint, 100 }; 101 102 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 103 const plat_psci_ops_t **psci_ops) 104 { 105 assert(psci_ops); 106 107 for (int cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu += 1) { 108 mmio_write_32(SUNXI_CPUCFG_RVBAR_LO_REG(cpu), 109 sec_entrypoint & 0xffffffff); 110 mmio_write_32(SUNXI_CPUCFG_RVBAR_HI_REG(cpu), 111 sec_entrypoint >> 32); 112 } 113 114 *psci_ops = &sunxi_psci_ops; 115 116 return 0; 117 } 118