1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <debug.h> 10 #include <delay_timer.h> 11 #include <gicv2.h> 12 #include <mmio.h> 13 #include <platform.h> 14 #include <platform_def.h> 15 #include <psci.h> 16 #include <sunxi_mmap.h> 17 #include <sunxi_cpucfg.h> 18 19 #define SUNXI_WDOG0_CTRL_REG (SUNXI_WDOG_BASE + 0x0010) 20 #define SUNXI_WDOG0_CFG_REG (SUNXI_WDOG_BASE + 0x0014) 21 #define SUNXI_WDOG0_MODE_REG (SUNXI_WDOG_BASE + 0x0018) 22 23 #include "sunxi_private.h" 24 25 #define mpidr_is_valid(mpidr) ( \ 26 MPIDR_AFFLVL3_VAL(mpidr) == 0 && \ 27 MPIDR_AFFLVL2_VAL(mpidr) == 0 && \ 28 MPIDR_AFFLVL1_VAL(mpidr) < PLATFORM_CLUSTER_COUNT && \ 29 MPIDR_AFFLVL0_VAL(mpidr) < PLATFORM_MAX_CPUS_PER_CLUSTER) 30 31 static int sunxi_pwr_domain_on(u_register_t mpidr) 32 { 33 if (mpidr_is_valid(mpidr) == 0) 34 return PSCI_E_INTERN_FAIL; 35 36 sunxi_cpu_on(MPIDR_AFFLVL1_VAL(mpidr), MPIDR_AFFLVL0_VAL(mpidr)); 37 38 return PSCI_E_SUCCESS; 39 } 40 41 static void sunxi_pwr_domain_off(const psci_power_state_t *target_state) 42 { 43 gicv2_cpuif_disable(); 44 } 45 46 static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state) 47 { 48 gicv2_pcpu_distif_init(); 49 gicv2_cpuif_enable(); 50 } 51 52 static void __dead2 sunxi_system_off(void) 53 { 54 /* Turn off all secondary CPUs */ 55 sunxi_disable_secondary_cpus(plat_my_core_pos()); 56 57 sunxi_power_down(); 58 } 59 60 static void __dead2 sunxi_system_reset(void) 61 { 62 /* Reset the whole system when the watchdog times out */ 63 mmio_write_32(SUNXI_WDOG0_CFG_REG, 1); 64 /* Enable the watchdog with the shortest timeout (0.5 seconds) */ 65 mmio_write_32(SUNXI_WDOG0_MODE_REG, (0 << 4) | 1); 66 /* Wait for twice the watchdog timeout before panicking */ 67 mdelay(1000); 68 69 ERROR("PSCI: System reset failed\n"); 70 wfi(); 71 panic(); 72 } 73 74 static int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint) 75 { 76 /* The non-secure entry point must be in DRAM */ 77 if (ns_entrypoint >= SUNXI_DRAM_BASE) 78 return PSCI_E_SUCCESS; 79 80 return PSCI_E_INVALID_ADDRESS; 81 } 82 83 static plat_psci_ops_t sunxi_psci_ops = { 84 .pwr_domain_on = sunxi_pwr_domain_on, 85 .pwr_domain_off = sunxi_pwr_domain_off, 86 .pwr_domain_on_finish = sunxi_pwr_domain_on_finish, 87 .system_off = sunxi_system_off, 88 .system_reset = sunxi_system_reset, 89 .validate_ns_entrypoint = sunxi_validate_ns_entrypoint, 90 }; 91 92 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 93 const plat_psci_ops_t **psci_ops) 94 { 95 assert(psci_ops); 96 97 for (int cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu += 1) { 98 mmio_write_32(SUNXI_CPUCFG_RVBAR_LO_REG(cpu), 99 sec_entrypoint & 0xffffffff); 100 mmio_write_32(SUNXI_CPUCFG_RVBAR_HI_REG(cpu), 101 sec_entrypoint >> 32); 102 } 103 104 *psci_ops = &sunxi_psci_ops; 105 106 return 0; 107 } 108