1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <drivers/delay_timer.h> 14 #include <lib/mmio.h> 15 #include <lib/utils_def.h> 16 #include <plat/common/platform.h> 17 18 #include <core_off_arisc.h> 19 #include <sunxi_cpucfg.h> 20 #include <sunxi_mmap.h> 21 #include <sunxi_private.h> 22 23 static void sunxi_cpu_disable_power(unsigned int cluster, unsigned int core) 24 { 25 if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0xff) 26 return; 27 28 VERBOSE("PSCI: Disabling power to cluster %d core %d\n", cluster, core); 29 30 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xff); 31 } 32 33 static void sunxi_cpu_enable_power(unsigned int cluster, unsigned int core) 34 { 35 if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0) 36 return; 37 38 VERBOSE("PSCI: Enabling power to cluster %d core %d\n", cluster, core); 39 40 /* Power enable sequence from original Allwinner sources */ 41 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xfe); 42 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xf8); 43 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xe0); 44 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x80); 45 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x00); 46 } 47 48 void sunxi_cpu_off(unsigned int cluster, unsigned int core) 49 { 50 int corenr = cluster * PLATFORM_MAX_CPUS_PER_CLUSTER + core; 51 52 VERBOSE("PSCI: Powering off cluster %d core %d\n", cluster, core); 53 54 /* Deassert DBGPWRDUP */ 55 mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); 56 57 /* We can't turn ourself off like this, but it works for other cores. */ 58 if (plat_my_core_pos() != corenr) { 59 /* Activate the core output clamps, but not for core 0. */ 60 if (corenr != 0) 61 mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster), 62 BIT(core)); 63 /* Assert CPU power-on reset */ 64 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); 65 /* Remove power from the CPU */ 66 sunxi_cpu_disable_power(cluster, core); 67 68 return; 69 } 70 71 /* Simplifies assembly, all SoCs so far are single cluster anyway. */ 72 assert(cluster == 0); 73 74 /* 75 * If we are supposed to turn ourself off, tell the arisc SCP 76 * to do that work for us. The code expects the core mask to be 77 * patched into the first instruction. 78 */ 79 sunxi_execute_arisc_code(arisc_core_off, sizeof(arisc_core_off), 80 0, BIT_32(core)); 81 } 82 83 void sunxi_cpu_on(unsigned int cluster, unsigned int core) 84 { 85 VERBOSE("PSCI: Powering on cluster %d core %d\n", cluster, core); 86 87 /* Assert CPU core reset */ 88 mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core)); 89 /* Assert CPU power-on reset */ 90 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); 91 /* Set CPU to start in AArch64 mode */ 92 mmio_setbits_32(SUNXI_CPUCFG_CLS_CTRL_REG0(cluster), BIT(24 + core)); 93 /* Apply power to the CPU */ 94 sunxi_cpu_enable_power(cluster, core); 95 /* Release the core output clamps */ 96 mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core)); 97 /* Deassert CPU power-on reset */ 98 mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); 99 /* Deassert CPU core reset */ 100 mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core)); 101 /* Assert DBGPWRDUP */ 102 mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); 103 } 104 105 void sunxi_disable_secondary_cpus(unsigned int primary_cpu) 106 { 107 for (unsigned int cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu += 1) { 108 if (cpu == primary_cpu) 109 continue; 110 sunxi_cpu_off(cpu / PLATFORM_MAX_CPUS_PER_CLUSTER, 111 cpu % PLATFORM_MAX_CPUS_PER_CLUSTER); 112 } 113 } 114