1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <errno.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <lib/mmio.h> 14 #include <lib/xlat_tables/xlat_tables_v2.h> 15 #include <plat/common/platform.h> 16 17 #include <sunxi_def.h> 18 #include <sunxi_mmap.h> 19 #include <sunxi_private.h> 20 21 static const mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = { 22 MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE, 23 MT_MEMORY | MT_RW | MT_SECURE), 24 MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE, 25 MT_DEVICE | MT_RW | MT_SECURE), 26 MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE, 27 MT_MEMORY | MT_RW | MT_SECURE), 28 MAP_REGION(PLAT_SUNXI_NS_IMAGE_OFFSET, 29 SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE, 30 SUNXI_DRAM_MAP_SIZE, 31 MT_MEMORY | MT_RO | MT_NS), 32 {}, 33 }; 34 35 unsigned int plat_get_syscnt_freq2(void) 36 { 37 return SUNXI_OSC24M_CLK_IN_HZ; 38 } 39 40 uintptr_t plat_get_ns_image_entrypoint(void) 41 { 42 #ifdef PRELOADED_BL33_BASE 43 return PRELOADED_BL33_BASE; 44 #else 45 return PLAT_SUNXI_NS_IMAGE_OFFSET; 46 #endif 47 } 48 49 void sunxi_configure_mmu_el3(int flags) 50 { 51 mmap_add_region(BL31_BASE, BL31_BASE, 52 BL31_LIMIT - BL31_BASE, 53 MT_MEMORY | MT_RW | MT_SECURE); 54 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 55 BL_CODE_END - BL_CODE_BASE, 56 MT_CODE | MT_SECURE); 57 mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, 58 BL_RO_DATA_END - BL_RO_DATA_BASE, 59 MT_RO_DATA | MT_SECURE); 60 mmap_add(sunxi_mmap); 61 init_xlat_tables(); 62 63 enable_mmu_el3(0); 64 } 65 66 #define SRAM_VER_REG (SUNXI_SYSCON_BASE + 0x24) 67 uint16_t sunxi_read_soc_id(void) 68 { 69 uint32_t reg = mmio_read_32(SRAM_VER_REG); 70 71 /* Set bit 15 to prepare for the SOCID read. */ 72 mmio_write_32(SRAM_VER_REG, reg | BIT(15)); 73 74 reg = mmio_read_32(SRAM_VER_REG); 75 76 /* deactivate the SOCID access again */ 77 mmio_write_32(SRAM_VER_REG, reg & ~BIT(15)); 78 79 return reg >> 16; 80 } 81 82 /* 83 * Configure a given pin to the GPIO-OUT function and sets its level. 84 * The port is given as a capital letter, the pin is the number within 85 * this port group. 86 * So to set pin PC7 to high, use: sunxi_set_gpio_out('C', 7, true); 87 */ 88 void sunxi_set_gpio_out(char port, int pin, bool level_high) 89 { 90 uintptr_t port_base; 91 92 if (port < 'A' || port > 'L') 93 return; 94 if (port == 'L') 95 port_base = SUNXI_R_PIO_BASE; 96 else 97 port_base = SUNXI_PIO_BASE + (port - 'A') * 0x24; 98 99 /* Set the new level first before configuring the pin. */ 100 if (level_high) 101 mmio_setbits_32(port_base + 0x10, BIT(pin)); 102 else 103 mmio_clrbits_32(port_base + 0x10, BIT(pin)); 104 105 /* configure pin as GPIO out (4(3) bits per pin, 1: GPIO out */ 106 mmio_clrsetbits_32(port_base + (pin / 8) * 4, 107 0x7 << ((pin % 8) * 4), 108 0x1 << ((pin % 8) * 4)); 109 } 110 111 int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb) 112 { 113 uint32_t pin_func = 0x77; 114 uint32_t device_bit; 115 unsigned int reset_offset = 0xb0; 116 117 switch (socid) { 118 case SUNXI_SOC_H5: 119 if (use_rsb) 120 return -ENODEV; 121 pin_func = 0x22; 122 device_bit = BIT(6); 123 break; 124 case SUNXI_SOC_H6: 125 if (use_rsb) 126 return -ENODEV; 127 pin_func = 0x33; 128 device_bit = BIT(16); 129 reset_offset = 0x19c; 130 break; 131 case SUNXI_SOC_A64: 132 pin_func = use_rsb ? 0x22 : 0x33; 133 device_bit = use_rsb ? BIT(3) : BIT(6); 134 break; 135 default: 136 INFO("R_I2C/RSB on Allwinner 0x%x SoC not supported\n", socid); 137 return -ENODEV; 138 } 139 140 /* un-gate R_PIO clock */ 141 if (socid != SUNXI_SOC_H6) 142 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, BIT(0)); 143 144 /* switch pins PL0 and PL1 to the desired function */ 145 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x00, 0xffU, pin_func); 146 147 /* level 2 drive strength */ 148 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x14, 0x0fU, 0xaU); 149 150 /* set both pins to pull-up */ 151 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x1c, 0x0fU, 0x5U); 152 153 /* assert, then de-assert reset of I2C/RSB controller */ 154 mmio_clrbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); 155 mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); 156 157 /* un-gate clock */ 158 if (socid != SUNXI_SOC_H6) 159 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit); 160 else 161 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x19c, device_bit | BIT(0)); 162 163 return 0; 164 } 165 166 /* This lock synchronises access to the arisc management processor. */ 167 DEFINE_BAKERY_LOCK(arisc_lock); 168 169 /* 170 * Tell the "arisc" SCP core (an OpenRISC core) to execute some code. 171 * We don't have any service running there, so we place some OpenRISC code 172 * in SRAM, put the address of that into the reset vector and release the 173 * arisc reset line. The SCP will execute that code and pull the line up again. 174 */ 175 void sunxi_execute_arisc_code(uint32_t *code, size_t size, 176 int patch_offset, uint16_t param) 177 { 178 uintptr_t arisc_reset_vec = SUNXI_SRAM_A2_BASE - 0x4000 + 0x100; 179 180 do { 181 bakery_lock_get(&arisc_lock); 182 /* Wait until the arisc is in reset state. */ 183 if (!(mmio_read_32(SUNXI_R_CPUCFG_BASE) & BIT(0))) 184 break; 185 186 bakery_lock_release(&arisc_lock); 187 } while (1); 188 189 /* Patch up the code to feed in an input parameter. */ 190 if (patch_offset >= 0 && patch_offset <= (size - 4)) 191 code[patch_offset] = (code[patch_offset] & ~0xffff) | param; 192 clean_dcache_range((uintptr_t)code, size); 193 194 /* 195 * The OpenRISC unconditional branch has opcode 0, the branch offset 196 * is in the lower 26 bits, containing the distance to the target, 197 * in instruction granularity (32 bits). 198 */ 199 mmio_write_32(arisc_reset_vec, ((uintptr_t)code - arisc_reset_vec) / 4); 200 clean_dcache_range(arisc_reset_vec, 4); 201 202 /* De-assert the arisc reset line to let it run. */ 203 mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0)); 204 205 /* 206 * We release the lock here, although the arisc is still busy. 207 * But as long as it runs, the reset line is high, so other users 208 * won't leave the loop above. 209 * Once it has finished, the code is supposed to clear the reset line, 210 * to signal this to other users. 211 */ 212 bakery_lock_release(&arisc_lock); 213 } 214