1 /* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <errno.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <lib/mmio.h> 14 #include <lib/xlat_tables/xlat_tables_v2.h> 15 #include <plat/common/platform.h> 16 17 #include <sunxi_def.h> 18 #include <sunxi_mmap.h> 19 #include <sunxi_private.h> 20 21 static const mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = { 22 MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE, 23 MT_RW_DATA | MT_SECURE), 24 MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE, 25 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER), 26 MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE, 27 MT_RW_DATA | MT_SECURE), 28 MAP_REGION(PLAT_SUNXI_NS_IMAGE_OFFSET, 29 SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE, 30 SUNXI_DRAM_MAP_SIZE, 31 MT_RO_DATA | MT_NS), 32 {}, 33 }; 34 35 unsigned int plat_get_syscnt_freq2(void) 36 { 37 return SUNXI_OSC24M_CLK_IN_HZ; 38 } 39 40 uintptr_t plat_get_ns_image_entrypoint(void) 41 { 42 #ifdef PRELOADED_BL33_BASE 43 return PRELOADED_BL33_BASE; 44 #else 45 return PLAT_SUNXI_NS_IMAGE_OFFSET; 46 #endif 47 } 48 49 void sunxi_configure_mmu_el3(int flags) 50 { 51 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 52 BL_CODE_END - BL_CODE_BASE, 53 MT_CODE | MT_SECURE); 54 mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, 55 BL_RO_DATA_END - BL_RO_DATA_BASE, 56 MT_RO_DATA | MT_SECURE); 57 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 58 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 59 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER); 60 61 mmap_add(sunxi_mmap); 62 init_xlat_tables(); 63 64 enable_mmu_el3(0); 65 } 66 67 #define SRAM_VER_REG (SUNXI_SYSCON_BASE + 0x24) 68 uint16_t sunxi_read_soc_id(void) 69 { 70 uint32_t reg = mmio_read_32(SRAM_VER_REG); 71 72 /* Set bit 15 to prepare for the SOCID read. */ 73 mmio_write_32(SRAM_VER_REG, reg | BIT(15)); 74 75 reg = mmio_read_32(SRAM_VER_REG); 76 77 /* deactivate the SOCID access again */ 78 mmio_write_32(SRAM_VER_REG, reg & ~BIT(15)); 79 80 return reg >> 16; 81 } 82 83 /* 84 * Configure a given pin to the GPIO-OUT function and sets its level. 85 * The port is given as a capital letter, the pin is the number within 86 * this port group. 87 * So to set pin PC7 to high, use: sunxi_set_gpio_out('C', 7, true); 88 */ 89 void sunxi_set_gpio_out(char port, int pin, bool level_high) 90 { 91 uintptr_t port_base; 92 93 if (port < 'A' || port > 'L') 94 return; 95 if (port == 'L') 96 port_base = SUNXI_R_PIO_BASE; 97 else 98 port_base = SUNXI_PIO_BASE + (port - 'A') * 0x24; 99 100 /* Set the new level first before configuring the pin. */ 101 if (level_high) 102 mmio_setbits_32(port_base + 0x10, BIT(pin)); 103 else 104 mmio_clrbits_32(port_base + 0x10, BIT(pin)); 105 106 /* configure pin as GPIO out (4(3) bits per pin, 1: GPIO out */ 107 mmio_clrsetbits_32(port_base + (pin / 8) * 4, 108 0x7 << ((pin % 8) * 4), 109 0x1 << ((pin % 8) * 4)); 110 } 111 112 int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb) 113 { 114 uint32_t pin_func = 0x77; 115 uint32_t device_bit; 116 unsigned int reset_offset = 0xb0; 117 118 switch (socid) { 119 case SUNXI_SOC_H5: 120 if (use_rsb) 121 return -ENODEV; 122 pin_func = 0x22; 123 device_bit = BIT(6); 124 break; 125 case SUNXI_SOC_H6: 126 if (use_rsb) 127 return -ENODEV; 128 pin_func = 0x33; 129 device_bit = BIT(16); 130 reset_offset = 0x19c; 131 break; 132 case SUNXI_SOC_A64: 133 pin_func = use_rsb ? 0x22 : 0x33; 134 device_bit = use_rsb ? BIT(3) : BIT(6); 135 break; 136 default: 137 INFO("R_I2C/RSB on Allwinner 0x%x SoC not supported\n", socid); 138 return -ENODEV; 139 } 140 141 /* un-gate R_PIO clock */ 142 if (socid != SUNXI_SOC_H6) 143 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, BIT(0)); 144 145 /* switch pins PL0 and PL1 to the desired function */ 146 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x00, 0xffU, pin_func); 147 148 /* level 2 drive strength */ 149 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x14, 0x0fU, 0xaU); 150 151 /* set both pins to pull-up */ 152 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x1c, 0x0fU, 0x5U); 153 154 /* un-gate clock */ 155 if (socid != SUNXI_SOC_H6) 156 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit); 157 else 158 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x19c, device_bit | BIT(0)); 159 160 /* assert, then de-assert reset of I2C/RSB controller */ 161 mmio_clrbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); 162 mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); 163 164 return 0; 165 } 166 167 /* This lock synchronises access to the arisc management processor. */ 168 DEFINE_BAKERY_LOCK(arisc_lock); 169 170 /* 171 * Tell the "arisc" SCP core (an OpenRISC core) to execute some code. 172 * We don't have any service running there, so we place some OpenRISC code 173 * in SRAM, put the address of that into the reset vector and release the 174 * arisc reset line. The SCP will execute that code and pull the line up again. 175 */ 176 void sunxi_execute_arisc_code(uint32_t *code, size_t size, uint16_t param) 177 { 178 uintptr_t arisc_reset_vec = SUNXI_SRAM_A2_BASE - 0x4000 + 0x100; 179 180 do { 181 bakery_lock_get(&arisc_lock); 182 /* Wait until the arisc is in reset state. */ 183 if (!(mmio_read_32(SUNXI_R_CPUCFG_BASE) & BIT(0))) 184 break; 185 186 bakery_lock_release(&arisc_lock); 187 } while (1); 188 189 /* Patch up the code to feed in an input parameter. */ 190 code[0] = (code[0] & ~0xffff) | param; 191 clean_dcache_range((uintptr_t)code, size); 192 193 /* 194 * The OpenRISC unconditional branch has opcode 0, the branch offset 195 * is in the lower 26 bits, containing the distance to the target, 196 * in instruction granularity (32 bits). 197 */ 198 mmio_write_32(arisc_reset_vec, ((uintptr_t)code - arisc_reset_vec) / 4); 199 clean_dcache_range(arisc_reset_vec, 4); 200 201 /* De-assert the arisc reset line to let it run. */ 202 mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0)); 203 204 /* 205 * We release the lock here, although the arisc is still busy. 206 * But as long as it runs, the reset line is high, so other users 207 * won't leave the loop above. 208 * Once it has finished, the code is supposed to clear the reset line, 209 * to signal this to other users. 210 */ 211 bakery_lock_release(&arisc_lock); 212 } 213