1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <debug.h> 8 #include <errno.h> 9 #include <mmio.h> 10 #include <platform.h> 11 #include <platform_def.h> 12 #include <sunxi_def.h> 13 #include <sunxi_private.h> 14 #include <xlat_tables_v2.h> 15 16 static mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = { 17 MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE, 18 MT_MEMORY | MT_RW | MT_SECURE), 19 MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE, 20 MT_DEVICE | MT_RW | MT_SECURE), 21 MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE, 22 MT_MEMORY | MT_RW | MT_SECURE), 23 MAP_REGION(PLAT_SUNXI_NS_IMAGE_OFFSET, 24 SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE, 25 SUNXI_DRAM_MAP_SIZE, 26 MT_MEMORY | MT_RO | MT_NS), 27 {}, 28 }; 29 30 unsigned int plat_get_syscnt_freq2(void) 31 { 32 return SUNXI_OSC24M_CLK_IN_HZ; 33 } 34 35 uintptr_t plat_get_ns_image_entrypoint(void) 36 { 37 #ifdef PRELOADED_BL33_BASE 38 return PRELOADED_BL33_BASE; 39 #else 40 return PLAT_SUNXI_NS_IMAGE_OFFSET; 41 #endif 42 } 43 44 void sunxi_configure_mmu_el3(int flags) 45 { 46 mmap_add_region(BL31_BASE, BL31_BASE, 47 BL31_LIMIT - BL31_BASE, 48 MT_MEMORY | MT_RW | MT_SECURE); 49 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 50 BL_CODE_END - BL_CODE_BASE, 51 MT_CODE | MT_SECURE); 52 mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, 53 BL_RO_DATA_END - BL_RO_DATA_BASE, 54 MT_RO_DATA | MT_SECURE); 55 mmap_add(sunxi_mmap); 56 init_xlat_tables(); 57 58 enable_mmu_el3(0); 59 } 60 61 #define SRAM_VER_REG (SUNXI_SYSCON_BASE + 0x24) 62 uint16_t sunxi_read_soc_id(void) 63 { 64 uint32_t reg = mmio_read_32(SRAM_VER_REG); 65 66 /* Set bit 15 to prepare for the SOCID read. */ 67 mmio_write_32(SRAM_VER_REG, reg | BIT(15)); 68 69 reg = mmio_read_32(SRAM_VER_REG); 70 71 /* deactivate the SOCID access again */ 72 mmio_write_32(SRAM_VER_REG, reg & ~BIT(15)); 73 74 return reg >> 16; 75 } 76 77 /* 78 * Configure a given pin to the GPIO-OUT function and sets its level. 79 * The port is given as a capital letter, the pin is the number within 80 * this port group. 81 * So to set pin PC7 to high, use: sunxi_set_gpio_out('C', 7, true); 82 */ 83 void sunxi_set_gpio_out(char port, int pin, bool level_high) 84 { 85 uintptr_t port_base; 86 87 if (port < 'A' || port > 'L') 88 return; 89 if (port == 'L') 90 port_base = SUNXI_R_PIO_BASE; 91 else 92 port_base = SUNXI_PIO_BASE + (port - 'A') * 0x24; 93 94 /* Set the new level first before configuring the pin. */ 95 if (level_high) 96 mmio_setbits_32(port_base + 0x10, BIT(pin)); 97 else 98 mmio_clrbits_32(port_base + 0x10, BIT(pin)); 99 100 /* configure pin as GPIO out (4(3) bits per pin, 1: GPIO out */ 101 mmio_clrsetbits_32(port_base + (pin / 8) * 4, 102 0x7 << ((pin % 8) * 4), 103 0x1 << ((pin % 8) * 4)); 104 } 105 106 int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb) 107 { 108 uint32_t pin_func = 0x77; 109 uint32_t device_bit; 110 unsigned int reset_offset = 0xb0; 111 112 switch (socid) { 113 case SUNXI_SOC_H5: 114 if (use_rsb) 115 return -ENODEV; 116 pin_func = 0x22; 117 device_bit = BIT(6); 118 break; 119 case SUNXI_SOC_H6: 120 if (use_rsb) 121 return -ENODEV; 122 pin_func = 0x33; 123 device_bit = BIT(16); 124 reset_offset = 0x19c; 125 break; 126 case SUNXI_SOC_A64: 127 pin_func = use_rsb ? 0x22 : 0x33; 128 device_bit = use_rsb ? BIT(3) : BIT(6); 129 break; 130 default: 131 INFO("R_I2C/RSB on Allwinner 0x%x SoC not supported\n", socid); 132 return -ENODEV; 133 } 134 135 /* un-gate R_PIO clock */ 136 if (socid != SUNXI_SOC_H6) 137 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, BIT(0)); 138 139 /* switch pins PL0 and PL1 to the desired function */ 140 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x00, 0xffU, pin_func); 141 142 /* level 2 drive strength */ 143 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x14, 0x0fU, 0xaU); 144 145 /* set both pins to pull-up */ 146 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x1c, 0x0fU, 0x5U); 147 148 /* assert, then de-assert reset of I2C/RSB controller */ 149 mmio_clrbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); 150 mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); 151 152 /* un-gate clock */ 153 if (socid != SUNXI_SOC_H6) 154 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit); 155 else 156 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x19c, device_bit | BIT(0)); 157 158 return 0; 159 } 160