1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <debug.h> 9 #include <errno.h> 10 #include <mmio.h> 11 #include <platform.h> 12 #include <platform_def.h> 13 #include <sunxi_def.h> 14 #include <sunxi_mmap.h> 15 #include <sunxi_private.h> 16 #include <xlat_tables_v2.h> 17 18 static mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = { 19 MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE, 20 MT_MEMORY | MT_RW | MT_SECURE), 21 MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE, 22 MT_DEVICE | MT_RW | MT_SECURE), 23 MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE, 24 MT_MEMORY | MT_RW | MT_SECURE), 25 MAP_REGION(PLAT_SUNXI_NS_IMAGE_OFFSET, 26 SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE, 27 SUNXI_DRAM_MAP_SIZE, 28 MT_MEMORY | MT_RO | MT_NS), 29 {}, 30 }; 31 32 unsigned int plat_get_syscnt_freq2(void) 33 { 34 return SUNXI_OSC24M_CLK_IN_HZ; 35 } 36 37 uintptr_t plat_get_ns_image_entrypoint(void) 38 { 39 #ifdef PRELOADED_BL33_BASE 40 return PRELOADED_BL33_BASE; 41 #else 42 return PLAT_SUNXI_NS_IMAGE_OFFSET; 43 #endif 44 } 45 46 void sunxi_configure_mmu_el3(int flags) 47 { 48 mmap_add_region(BL31_BASE, BL31_BASE, 49 BL31_LIMIT - BL31_BASE, 50 MT_MEMORY | MT_RW | MT_SECURE); 51 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 52 BL_CODE_END - BL_CODE_BASE, 53 MT_CODE | MT_SECURE); 54 mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, 55 BL_RO_DATA_END - BL_RO_DATA_BASE, 56 MT_RO_DATA | MT_SECURE); 57 mmap_add(sunxi_mmap); 58 init_xlat_tables(); 59 60 enable_mmu_el3(0); 61 } 62 63 #define SRAM_VER_REG (SUNXI_SYSCON_BASE + 0x24) 64 uint16_t sunxi_read_soc_id(void) 65 { 66 uint32_t reg = mmio_read_32(SRAM_VER_REG); 67 68 /* Set bit 15 to prepare for the SOCID read. */ 69 mmio_write_32(SRAM_VER_REG, reg | BIT(15)); 70 71 reg = mmio_read_32(SRAM_VER_REG); 72 73 /* deactivate the SOCID access again */ 74 mmio_write_32(SRAM_VER_REG, reg & ~BIT(15)); 75 76 return reg >> 16; 77 } 78 79 /* 80 * Configure a given pin to the GPIO-OUT function and sets its level. 81 * The port is given as a capital letter, the pin is the number within 82 * this port group. 83 * So to set pin PC7 to high, use: sunxi_set_gpio_out('C', 7, true); 84 */ 85 void sunxi_set_gpio_out(char port, int pin, bool level_high) 86 { 87 uintptr_t port_base; 88 89 if (port < 'A' || port > 'L') 90 return; 91 if (port == 'L') 92 port_base = SUNXI_R_PIO_BASE; 93 else 94 port_base = SUNXI_PIO_BASE + (port - 'A') * 0x24; 95 96 /* Set the new level first before configuring the pin. */ 97 if (level_high) 98 mmio_setbits_32(port_base + 0x10, BIT(pin)); 99 else 100 mmio_clrbits_32(port_base + 0x10, BIT(pin)); 101 102 /* configure pin as GPIO out (4(3) bits per pin, 1: GPIO out */ 103 mmio_clrsetbits_32(port_base + (pin / 8) * 4, 104 0x7 << ((pin % 8) * 4), 105 0x1 << ((pin % 8) * 4)); 106 } 107 108 int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb) 109 { 110 uint32_t pin_func = 0x77; 111 uint32_t device_bit; 112 unsigned int reset_offset = 0xb0; 113 114 switch (socid) { 115 case SUNXI_SOC_H5: 116 if (use_rsb) 117 return -ENODEV; 118 pin_func = 0x22; 119 device_bit = BIT(6); 120 break; 121 case SUNXI_SOC_H6: 122 if (use_rsb) 123 return -ENODEV; 124 pin_func = 0x33; 125 device_bit = BIT(16); 126 reset_offset = 0x19c; 127 break; 128 case SUNXI_SOC_A64: 129 pin_func = use_rsb ? 0x22 : 0x33; 130 device_bit = use_rsb ? BIT(3) : BIT(6); 131 break; 132 default: 133 INFO("R_I2C/RSB on Allwinner 0x%x SoC not supported\n", socid); 134 return -ENODEV; 135 } 136 137 /* un-gate R_PIO clock */ 138 if (socid != SUNXI_SOC_H6) 139 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, BIT(0)); 140 141 /* switch pins PL0 and PL1 to the desired function */ 142 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x00, 0xffU, pin_func); 143 144 /* level 2 drive strength */ 145 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x14, 0x0fU, 0xaU); 146 147 /* set both pins to pull-up */ 148 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x1c, 0x0fU, 0x5U); 149 150 /* assert, then de-assert reset of I2C/RSB controller */ 151 mmio_clrbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); 152 mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); 153 154 /* un-gate clock */ 155 if (socid != SUNXI_SOC_H6) 156 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit); 157 else 158 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x19c, device_bit | BIT(0)); 159 160 return 0; 161 } 162 163 /* This lock synchronises access to the arisc management processor. */ 164 DEFINE_BAKERY_LOCK(arisc_lock); 165 166 /* 167 * Tell the "arisc" SCP core (an OpenRISC core) to execute some code. 168 * We don't have any service running there, so we place some OpenRISC code 169 * in SRAM, put the address of that into the reset vector and release the 170 * arisc reset line. The SCP will execute that code and pull the line up again. 171 */ 172 void sunxi_execute_arisc_code(uint32_t *code, size_t size, 173 int patch_offset, uint16_t param) 174 { 175 uintptr_t arisc_reset_vec = SUNXI_SRAM_A2_BASE - 0x4000 + 0x100; 176 177 do { 178 bakery_lock_get(&arisc_lock); 179 /* Wait until the arisc is in reset state. */ 180 if (!(mmio_read_32(SUNXI_R_CPUCFG_BASE) & BIT(0))) 181 break; 182 183 bakery_lock_release(&arisc_lock); 184 } while (1); 185 186 /* Patch up the code to feed in an input parameter. */ 187 if (patch_offset >= 0 && patch_offset <= (size - 4)) 188 code[patch_offset] = (code[patch_offset] & ~0xffff) | param; 189 clean_dcache_range((uintptr_t)code, size); 190 191 /* 192 * The OpenRISC unconditional branch has opcode 0, the branch offset 193 * is in the lower 26 bits, containing the distance to the target, 194 * in instruction granularity (32 bits). 195 */ 196 mmio_write_32(arisc_reset_vec, ((uintptr_t)code - arisc_reset_vec) / 4); 197 clean_dcache_range(arisc_reset_vec, 4); 198 199 /* De-assert the arisc reset line to let it run. */ 200 mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0)); 201 202 /* 203 * We release the lock here, although the arisc is still busy. 204 * But as long as it runs, the reset line is high, so other users 205 * won't leave the loop above. 206 * Once it has finished, the code is supposed to clear the reset line, 207 * to signal this to other users. 208 */ 209 bakery_lock_release(&arisc_lock); 210 } 211