1 /* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <errno.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <lib/mmio.h> 14 #include <lib/xlat_tables/xlat_tables_v2.h> 15 #include <plat/common/platform.h> 16 17 #include <sunxi_def.h> 18 #include <sunxi_mmap.h> 19 #include <sunxi_private.h> 20 21 static const mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = { 22 MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE, 23 MT_RW_DATA | MT_SECURE), 24 MAP_REGION_FLAT(SUNXI_SCP_BASE, SUNXI_SCP_SIZE, 25 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER), 26 MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE, 27 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER), 28 MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE, 29 MT_RW_DATA | MT_SECURE), 30 MAP_REGION(PLAT_SUNXI_NS_IMAGE_OFFSET, 31 SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE, 32 SUNXI_DRAM_MAP_SIZE, 33 MT_RO_DATA | MT_NS), 34 {}, 35 }; 36 37 unsigned int plat_get_syscnt_freq2(void) 38 { 39 return SUNXI_OSC24M_CLK_IN_HZ; 40 } 41 42 uintptr_t plat_get_ns_image_entrypoint(void) 43 { 44 #ifdef PRELOADED_BL33_BASE 45 return PRELOADED_BL33_BASE; 46 #else 47 return PLAT_SUNXI_NS_IMAGE_OFFSET; 48 #endif 49 } 50 51 void sunxi_configure_mmu_el3(int flags) 52 { 53 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 54 BL_CODE_END - BL_CODE_BASE, 55 MT_CODE | MT_SECURE); 56 mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, 57 BL_RO_DATA_END - BL_RO_DATA_BASE, 58 MT_RO_DATA | MT_SECURE); 59 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 60 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 61 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER); 62 63 mmap_add(sunxi_mmap); 64 init_xlat_tables(); 65 66 enable_mmu_el3(0); 67 } 68 69 #define SRAM_VER_REG (SUNXI_SYSCON_BASE + 0x24) 70 uint16_t sunxi_read_soc_id(void) 71 { 72 uint32_t reg = mmio_read_32(SRAM_VER_REG); 73 74 /* Set bit 15 to prepare for the SOCID read. */ 75 mmio_write_32(SRAM_VER_REG, reg | BIT(15)); 76 77 reg = mmio_read_32(SRAM_VER_REG); 78 79 /* deactivate the SOCID access again */ 80 mmio_write_32(SRAM_VER_REG, reg & ~BIT(15)); 81 82 return reg >> 16; 83 } 84 85 /* 86 * Configure a given pin to the GPIO-OUT function and sets its level. 87 * The port is given as a capital letter, the pin is the number within 88 * this port group. 89 * So to set pin PC7 to high, use: sunxi_set_gpio_out('C', 7, true); 90 */ 91 void sunxi_set_gpio_out(char port, int pin, bool level_high) 92 { 93 uintptr_t port_base; 94 95 if (port < 'A' || port > 'L') 96 return; 97 if (port == 'L') 98 port_base = SUNXI_R_PIO_BASE; 99 else 100 port_base = SUNXI_PIO_BASE + (port - 'A') * 0x24; 101 102 /* Set the new level first before configuring the pin. */ 103 if (level_high) 104 mmio_setbits_32(port_base + 0x10, BIT(pin)); 105 else 106 mmio_clrbits_32(port_base + 0x10, BIT(pin)); 107 108 /* configure pin as GPIO out (4(3) bits per pin, 1: GPIO out */ 109 mmio_clrsetbits_32(port_base + (pin / 8) * 4, 110 0x7 << ((pin % 8) * 4), 111 0x1 << ((pin % 8) * 4)); 112 } 113 114 int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb) 115 { 116 uint32_t pin_func = 0x77; 117 uint32_t device_bit; 118 unsigned int reset_offset = 0xb0; 119 120 switch (socid) { 121 case SUNXI_SOC_H5: 122 if (use_rsb) 123 return -ENODEV; 124 pin_func = 0x22; 125 device_bit = BIT(6); 126 break; 127 case SUNXI_SOC_H6: 128 if (use_rsb) 129 return -ENODEV; 130 pin_func = 0x33; 131 device_bit = BIT(16); 132 reset_offset = 0x19c; 133 break; 134 case SUNXI_SOC_A64: 135 pin_func = use_rsb ? 0x22 : 0x33; 136 device_bit = use_rsb ? BIT(3) : BIT(6); 137 break; 138 default: 139 INFO("R_I2C/RSB on Allwinner 0x%x SoC not supported\n", socid); 140 return -ENODEV; 141 } 142 143 /* un-gate R_PIO clock */ 144 if (socid != SUNXI_SOC_H6) 145 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, BIT(0)); 146 147 /* switch pins PL0 and PL1 to the desired function */ 148 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x00, 0xffU, pin_func); 149 150 /* level 2 drive strength */ 151 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x14, 0x0fU, 0xaU); 152 153 /* set both pins to pull-up */ 154 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x1c, 0x0fU, 0x5U); 155 156 /* un-gate clock */ 157 if (socid != SUNXI_SOC_H6) 158 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit); 159 else 160 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x19c, device_bit | BIT(0)); 161 162 /* assert, then de-assert reset of I2C/RSB controller */ 163 mmio_clrbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); 164 mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); 165 166 return 0; 167 } 168 169 /* This lock synchronises access to the arisc management processor. */ 170 DEFINE_BAKERY_LOCK(arisc_lock); 171 172 /* 173 * Tell the "arisc" SCP core (an OpenRISC core) to execute some code. 174 * We don't have any service running there, so we place some OpenRISC code 175 * in SRAM, put the address of that into the reset vector and release the 176 * arisc reset line. The SCP will execute that code and pull the line up again. 177 */ 178 void sunxi_execute_arisc_code(uint32_t *code, size_t size, uint16_t param) 179 { 180 uintptr_t arisc_reset_vec = SUNXI_SRAM_A2_BASE + 0x100; 181 182 do { 183 bakery_lock_get(&arisc_lock); 184 /* Wait until the arisc is in reset state. */ 185 if (!(mmio_read_32(SUNXI_R_CPUCFG_BASE) & BIT(0))) 186 break; 187 188 bakery_lock_release(&arisc_lock); 189 } while (1); 190 191 /* Patch up the code to feed in an input parameter. */ 192 code[0] = (code[0] & ~0xffff) | param; 193 clean_dcache_range((uintptr_t)code, size); 194 195 /* 196 * The OpenRISC unconditional branch has opcode 0, the branch offset 197 * is in the lower 26 bits, containing the distance to the target, 198 * in instruction granularity (32 bits). 199 */ 200 mmio_write_32(arisc_reset_vec, ((uintptr_t)code - arisc_reset_vec) / 4); 201 clean_dcache_range(arisc_reset_vec, 4); 202 203 /* De-assert the arisc reset line to let it run. */ 204 mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0)); 205 206 /* 207 * We release the lock here, although the arisc is still busy. 208 * But as long as it runs, the reset line is high, so other users 209 * won't leave the loop above. 210 * Once it has finished, the code is supposed to clear the reset line, 211 * to signal this to other users. 212 */ 213 bakery_lock_release(&arisc_lock); 214 } 215