1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <mmio.h> 8 #include <platform.h> 9 #include <platform_def.h> 10 #include <sunxi_def.h> 11 #include <xlat_tables_v2.h> 12 13 #include "sunxi_private.h" 14 15 static mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = { 16 MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE, 17 MT_MEMORY | MT_RW | MT_SECURE), 18 MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE, 19 MT_DEVICE | MT_RW | MT_SECURE), 20 MAP_REGION_FLAT(SUNXI_DRAM_BASE, SUNXI_DRAM_SIZE, 21 MT_MEMORY | MT_RW | MT_NS), 22 {}, 23 }; 24 25 unsigned int plat_get_syscnt_freq2(void) 26 { 27 return SUNXI_OSC24M_CLK_IN_HZ; 28 } 29 30 uintptr_t plat_get_ns_image_entrypoint(void) 31 { 32 #ifdef PRELOADED_BL33_BASE 33 return PRELOADED_BL33_BASE; 34 #else 35 return PLAT_SUNXI_NS_IMAGE_OFFSET; 36 #endif 37 } 38 39 void sunxi_configure_mmu_el3(int flags) 40 { 41 mmap_add_region(BL31_BASE, BL31_BASE, 42 BL31_LIMIT - BL31_BASE, 43 MT_MEMORY | MT_RW | MT_SECURE); 44 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 45 BL_CODE_END - BL_CODE_BASE, 46 MT_CODE | MT_SECURE); 47 mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, 48 BL_RO_DATA_END - BL_RO_DATA_BASE, 49 MT_RO_DATA | MT_SECURE); 50 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 51 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 52 MT_DEVICE | MT_RW | MT_SECURE); 53 mmap_add(sunxi_mmap); 54 init_xlat_tables(); 55 56 enable_mmu_el3(0); 57 } 58 59 #define SRAM_VER_REG (SUNXI_SYSCON_BASE + 0x24) 60 uint16_t sunxi_read_soc_id(void) 61 { 62 uint32_t reg = mmio_read_32(SRAM_VER_REG); 63 64 /* Set bit 15 to prepare for the SOCID read. */ 65 mmio_write_32(SRAM_VER_REG, reg | BIT(15)); 66 67 reg = mmio_read_32(SRAM_VER_REG); 68 69 /* deactivate the SOCID access again */ 70 mmio_write_32(SRAM_VER_REG, reg & ~BIT(15)); 71 72 return reg >> 16; 73 } 74