1 /* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <errno.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <lib/mmio.h> 14 #include <lib/xlat_tables/xlat_tables_v2.h> 15 #include <plat/common/platform.h> 16 17 #include <sunxi_def.h> 18 #include <sunxi_mmap.h> 19 #include <sunxi_private.h> 20 21 static const mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = { 22 MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE, 23 MT_MEMORY | MT_RW | MT_SECURE), 24 MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE, 25 MT_DEVICE | MT_RW | MT_SECURE), 26 MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE, 27 MT_MEMORY | MT_RW | MT_SECURE), 28 MAP_REGION(PLAT_SUNXI_NS_IMAGE_OFFSET, 29 SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE, 30 SUNXI_DRAM_MAP_SIZE, 31 MT_MEMORY | MT_RO | MT_NS), 32 {}, 33 }; 34 35 unsigned int plat_get_syscnt_freq2(void) 36 { 37 return SUNXI_OSC24M_CLK_IN_HZ; 38 } 39 40 uintptr_t plat_get_ns_image_entrypoint(void) 41 { 42 #ifdef PRELOADED_BL33_BASE 43 return PRELOADED_BL33_BASE; 44 #else 45 return PLAT_SUNXI_NS_IMAGE_OFFSET; 46 #endif 47 } 48 49 void sunxi_configure_mmu_el3(int flags) 50 { 51 mmap_add_region(BL31_BASE, BL31_BASE, 52 BL31_LIMIT - BL31_BASE, 53 MT_MEMORY | MT_RW | MT_SECURE); 54 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 55 BL_CODE_END - BL_CODE_BASE, 56 MT_CODE | MT_SECURE); 57 mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, 58 BL_RO_DATA_END - BL_RO_DATA_BASE, 59 MT_RO_DATA | MT_SECURE); 60 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 61 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 62 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER); 63 64 mmap_add(sunxi_mmap); 65 init_xlat_tables(); 66 67 enable_mmu_el3(0); 68 } 69 70 #define SRAM_VER_REG (SUNXI_SYSCON_BASE + 0x24) 71 uint16_t sunxi_read_soc_id(void) 72 { 73 uint32_t reg = mmio_read_32(SRAM_VER_REG); 74 75 /* Set bit 15 to prepare for the SOCID read. */ 76 mmio_write_32(SRAM_VER_REG, reg | BIT(15)); 77 78 reg = mmio_read_32(SRAM_VER_REG); 79 80 /* deactivate the SOCID access again */ 81 mmio_write_32(SRAM_VER_REG, reg & ~BIT(15)); 82 83 return reg >> 16; 84 } 85 86 /* 87 * Configure a given pin to the GPIO-OUT function and sets its level. 88 * The port is given as a capital letter, the pin is the number within 89 * this port group. 90 * So to set pin PC7 to high, use: sunxi_set_gpio_out('C', 7, true); 91 */ 92 void sunxi_set_gpio_out(char port, int pin, bool level_high) 93 { 94 uintptr_t port_base; 95 96 if (port < 'A' || port > 'L') 97 return; 98 if (port == 'L') 99 port_base = SUNXI_R_PIO_BASE; 100 else 101 port_base = SUNXI_PIO_BASE + (port - 'A') * 0x24; 102 103 /* Set the new level first before configuring the pin. */ 104 if (level_high) 105 mmio_setbits_32(port_base + 0x10, BIT(pin)); 106 else 107 mmio_clrbits_32(port_base + 0x10, BIT(pin)); 108 109 /* configure pin as GPIO out (4(3) bits per pin, 1: GPIO out */ 110 mmio_clrsetbits_32(port_base + (pin / 8) * 4, 111 0x7 << ((pin % 8) * 4), 112 0x1 << ((pin % 8) * 4)); 113 } 114 115 int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb) 116 { 117 uint32_t pin_func = 0x77; 118 uint32_t device_bit; 119 unsigned int reset_offset = 0xb0; 120 121 switch (socid) { 122 case SUNXI_SOC_H5: 123 if (use_rsb) 124 return -ENODEV; 125 pin_func = 0x22; 126 device_bit = BIT(6); 127 break; 128 case SUNXI_SOC_H6: 129 if (use_rsb) 130 return -ENODEV; 131 pin_func = 0x33; 132 device_bit = BIT(16); 133 reset_offset = 0x19c; 134 break; 135 case SUNXI_SOC_A64: 136 pin_func = use_rsb ? 0x22 : 0x33; 137 device_bit = use_rsb ? BIT(3) : BIT(6); 138 break; 139 default: 140 INFO("R_I2C/RSB on Allwinner 0x%x SoC not supported\n", socid); 141 return -ENODEV; 142 } 143 144 /* un-gate R_PIO clock */ 145 if (socid != SUNXI_SOC_H6) 146 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, BIT(0)); 147 148 /* switch pins PL0 and PL1 to the desired function */ 149 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x00, 0xffU, pin_func); 150 151 /* level 2 drive strength */ 152 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x14, 0x0fU, 0xaU); 153 154 /* set both pins to pull-up */ 155 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x1c, 0x0fU, 0x5U); 156 157 /* un-gate clock */ 158 if (socid != SUNXI_SOC_H6) 159 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit); 160 else 161 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x19c, device_bit | BIT(0)); 162 163 /* assert, then de-assert reset of I2C/RSB controller */ 164 mmio_clrbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); 165 mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); 166 167 return 0; 168 } 169 170 /* This lock synchronises access to the arisc management processor. */ 171 DEFINE_BAKERY_LOCK(arisc_lock); 172 173 /* 174 * Tell the "arisc" SCP core (an OpenRISC core) to execute some code. 175 * We don't have any service running there, so we place some OpenRISC code 176 * in SRAM, put the address of that into the reset vector and release the 177 * arisc reset line. The SCP will execute that code and pull the line up again. 178 */ 179 void sunxi_execute_arisc_code(uint32_t *code, size_t size, uint16_t param) 180 { 181 uintptr_t arisc_reset_vec = SUNXI_SRAM_A2_BASE - 0x4000 + 0x100; 182 183 do { 184 bakery_lock_get(&arisc_lock); 185 /* Wait until the arisc is in reset state. */ 186 if (!(mmio_read_32(SUNXI_R_CPUCFG_BASE) & BIT(0))) 187 break; 188 189 bakery_lock_release(&arisc_lock); 190 } while (1); 191 192 /* Patch up the code to feed in an input parameter. */ 193 code[0] = (code[0] & ~0xffff) | param; 194 clean_dcache_range((uintptr_t)code, size); 195 196 /* 197 * The OpenRISC unconditional branch has opcode 0, the branch offset 198 * is in the lower 26 bits, containing the distance to the target, 199 * in instruction granularity (32 bits). 200 */ 201 mmio_write_32(arisc_reset_vec, ((uintptr_t)code - arisc_reset_vec) / 4); 202 clean_dcache_range(arisc_reset_vec, 4); 203 204 /* De-assert the arisc reset line to let it run. */ 205 mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0)); 206 207 /* 208 * We release the lock here, although the arisc is still busy. 209 * But as long as it runs, the reset line is high, so other users 210 * won't leave the loop above. 211 * Once it has finished, the code is supposed to clear the reset line, 212 * to signal this to other users. 213 */ 214 bakery_lock_release(&arisc_lock); 215 } 216