1*58032586SSamuel Holland /* 2*58032586SSamuel Holland * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3*58032586SSamuel Holland * 4*58032586SSamuel Holland * SPDX-License-Identifier: BSD-3-Clause 5*58032586SSamuel Holland */ 6*58032586SSamuel Holland 7*58032586SSamuel Holland #include <platform.h> 8*58032586SSamuel Holland #include <platform_def.h> 9*58032586SSamuel Holland #include <sunxi_def.h> 10*58032586SSamuel Holland #include <xlat_tables_v2.h> 11*58032586SSamuel Holland 12*58032586SSamuel Holland static mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = { 13*58032586SSamuel Holland MAP_REGION_FLAT(SUNXI_ROM_BASE, SUNXI_ROM_SIZE, 14*58032586SSamuel Holland MT_MEMORY | MT_RO | MT_SECURE), 15*58032586SSamuel Holland MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE, 16*58032586SSamuel Holland MT_MEMORY | MT_RW | MT_SECURE), 17*58032586SSamuel Holland MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE, 18*58032586SSamuel Holland MT_DEVICE | MT_RW | MT_SECURE), 19*58032586SSamuel Holland MAP_REGION_FLAT(SUNXI_DRAM_BASE, SUNXI_DRAM_SIZE, 20*58032586SSamuel Holland MT_MEMORY | MT_RW | MT_NS), 21*58032586SSamuel Holland {}, 22*58032586SSamuel Holland }; 23*58032586SSamuel Holland 24*58032586SSamuel Holland unsigned int plat_get_syscnt_freq2(void) 25*58032586SSamuel Holland { 26*58032586SSamuel Holland return SUNXI_OSC24M_CLK_IN_HZ; 27*58032586SSamuel Holland } 28*58032586SSamuel Holland 29*58032586SSamuel Holland uintptr_t plat_get_ns_image_entrypoint(void) 30*58032586SSamuel Holland { 31*58032586SSamuel Holland #ifdef PRELOADED_BL33_BASE 32*58032586SSamuel Holland return PRELOADED_BL33_BASE; 33*58032586SSamuel Holland #else 34*58032586SSamuel Holland return PLAT_SUNXI_NS_IMAGE_OFFSET; 35*58032586SSamuel Holland #endif 36*58032586SSamuel Holland } 37*58032586SSamuel Holland 38*58032586SSamuel Holland void sunxi_configure_mmu_el3(int flags) 39*58032586SSamuel Holland { 40*58032586SSamuel Holland mmap_add_region(BL31_BASE, BL31_BASE, 41*58032586SSamuel Holland BL31_LIMIT - BL31_BASE, 42*58032586SSamuel Holland MT_MEMORY | MT_RW | MT_SECURE); 43*58032586SSamuel Holland mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 44*58032586SSamuel Holland BL_CODE_END - BL_CODE_BASE, 45*58032586SSamuel Holland MT_CODE | MT_SECURE); 46*58032586SSamuel Holland mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, 47*58032586SSamuel Holland BL_RO_DATA_END - BL_RO_DATA_BASE, 48*58032586SSamuel Holland MT_RO_DATA | MT_SECURE); 49*58032586SSamuel Holland mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 50*58032586SSamuel Holland BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 51*58032586SSamuel Holland MT_DEVICE | MT_RW | MT_SECURE); 52*58032586SSamuel Holland mmap_add(sunxi_mmap); 53*58032586SSamuel Holland init_xlat_tables(); 54*58032586SSamuel Holland 55*58032586SSamuel Holland enable_mmu_el3(0); 56*58032586SSamuel Holland } 57