158032586SSamuel Holland /* 258032586SSamuel Holland * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 358032586SSamuel Holland * 458032586SSamuel Holland * SPDX-License-Identifier: BSD-3-Clause 558032586SSamuel Holland */ 658032586SSamuel Holland 7c4143b74SAndre Przywara #include <mmio.h> 858032586SSamuel Holland #include <platform.h> 958032586SSamuel Holland #include <platform_def.h> 1058032586SSamuel Holland #include <sunxi_def.h> 11*4ec1a239SAndre Przywara #include <sunxi_private.h> 1258032586SSamuel Holland #include <xlat_tables_v2.h> 1358032586SSamuel Holland 1458032586SSamuel Holland static mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = { 1558032586SSamuel Holland MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE, 1658032586SSamuel Holland MT_MEMORY | MT_RW | MT_SECURE), 1758032586SSamuel Holland MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE, 1858032586SSamuel Holland MT_DEVICE | MT_RW | MT_SECURE), 19c3af6b00SAndre Przywara MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE, 20c3af6b00SAndre Przywara MT_MEMORY | MT_RW | MT_SECURE), 21c3af6b00SAndre Przywara MAP_REGION(PLAT_SUNXI_NS_IMAGE_OFFSET, 22c3af6b00SAndre Przywara SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE, 23c3af6b00SAndre Przywara SUNXI_DRAM_MAP_SIZE, 24c3af6b00SAndre Przywara MT_MEMORY | MT_RO | MT_NS), 2558032586SSamuel Holland {}, 2658032586SSamuel Holland }; 2758032586SSamuel Holland 2858032586SSamuel Holland unsigned int plat_get_syscnt_freq2(void) 2958032586SSamuel Holland { 3058032586SSamuel Holland return SUNXI_OSC24M_CLK_IN_HZ; 3158032586SSamuel Holland } 3258032586SSamuel Holland 3358032586SSamuel Holland uintptr_t plat_get_ns_image_entrypoint(void) 3458032586SSamuel Holland { 3558032586SSamuel Holland #ifdef PRELOADED_BL33_BASE 3658032586SSamuel Holland return PRELOADED_BL33_BASE; 3758032586SSamuel Holland #else 3858032586SSamuel Holland return PLAT_SUNXI_NS_IMAGE_OFFSET; 3958032586SSamuel Holland #endif 4058032586SSamuel Holland } 4158032586SSamuel Holland 4258032586SSamuel Holland void sunxi_configure_mmu_el3(int flags) 4358032586SSamuel Holland { 4458032586SSamuel Holland mmap_add_region(BL31_BASE, BL31_BASE, 4558032586SSamuel Holland BL31_LIMIT - BL31_BASE, 4658032586SSamuel Holland MT_MEMORY | MT_RW | MT_SECURE); 4758032586SSamuel Holland mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 4858032586SSamuel Holland BL_CODE_END - BL_CODE_BASE, 4958032586SSamuel Holland MT_CODE | MT_SECURE); 5058032586SSamuel Holland mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, 5158032586SSamuel Holland BL_RO_DATA_END - BL_RO_DATA_BASE, 5258032586SSamuel Holland MT_RO_DATA | MT_SECURE); 5358032586SSamuel Holland mmap_add(sunxi_mmap); 5458032586SSamuel Holland init_xlat_tables(); 5558032586SSamuel Holland 5658032586SSamuel Holland enable_mmu_el3(0); 5758032586SSamuel Holland } 58c4143b74SAndre Przywara 59c4143b74SAndre Przywara #define SRAM_VER_REG (SUNXI_SYSCON_BASE + 0x24) 60c4143b74SAndre Przywara uint16_t sunxi_read_soc_id(void) 61c4143b74SAndre Przywara { 62c4143b74SAndre Przywara uint32_t reg = mmio_read_32(SRAM_VER_REG); 63c4143b74SAndre Przywara 64c4143b74SAndre Przywara /* Set bit 15 to prepare for the SOCID read. */ 65c4143b74SAndre Przywara mmio_write_32(SRAM_VER_REG, reg | BIT(15)); 66c4143b74SAndre Przywara 67c4143b74SAndre Przywara reg = mmio_read_32(SRAM_VER_REG); 68c4143b74SAndre Przywara 69c4143b74SAndre Przywara /* deactivate the SOCID access again */ 70c4143b74SAndre Przywara mmio_write_32(SRAM_VER_REG, reg & ~BIT(15)); 71c4143b74SAndre Przywara 72c4143b74SAndre Przywara return reg >> 16; 73c4143b74SAndre Przywara } 74