1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <libfdt.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <common/debug.h> 15 #include <drivers/arm/gicv2.h> 16 #include <drivers/console.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/ti/uart/uart_16550.h> 19 #include <lib/mmio.h> 20 #include <plat/common/platform.h> 21 22 #include <sunxi_def.h> 23 #include <sunxi_mmap.h> 24 #include <sunxi_private.h> 25 26 27 static entry_point_info_t bl32_image_ep_info; 28 static entry_point_info_t bl33_image_ep_info; 29 30 static console_16550_t console; 31 32 static const gicv2_driver_data_t sunxi_gic_data = { 33 .gicd_base = SUNXI_GICD_BASE, 34 .gicc_base = SUNXI_GICC_BASE, 35 }; 36 37 /* 38 * Try to find a DTB loaded in memory by previous stages. 39 * 40 * At the moment we implement a heuristic to find the DTB attached to U-Boot: 41 * U-Boot appends its DTB to the end of the image. Assuming that BL33 is 42 * U-Boot, try to find the size of the U-Boot image to learn the DTB address. 43 * The generic ARMv8 U-Boot image contains the load address and its size 44 * as u64 variables at the beginning of the image. There might be padding 45 * or other headers before that data, so scan the first 2KB after the BL33 46 * entry point to find the load address, which should be followed by the 47 * size. Adding those together gives us the address of the DTB. 48 */ 49 static void *sunxi_find_dtb(void) 50 { 51 uint64_t *u_boot_base; 52 int i; 53 54 u_boot_base = (void *)(SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE); 55 56 for (i = 0; i < 2048 / sizeof(uint64_t); i++) { 57 uint32_t *dtb_base; 58 59 if (u_boot_base[i] != PLAT_SUNXI_NS_IMAGE_OFFSET) 60 continue; 61 62 /* Does the suspected U-Boot size look anyhow reasonable? */ 63 if (u_boot_base[i + 1] >= 256 * 1024 * 1024) 64 continue; 65 66 /* end of the image: base address + size */ 67 dtb_base = (void *)((char *)u_boot_base + u_boot_base[i + 1]); 68 69 if (fdt_check_header(dtb_base) != 0) 70 continue; 71 72 return dtb_base; 73 } 74 75 return NULL; 76 } 77 78 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 79 u_register_t arg2, u_register_t arg3) 80 { 81 /* Initialize the debug console as soon as possible */ 82 console_16550_register(SUNXI_UART0_BASE, SUNXI_UART0_CLK_IN_HZ, 83 SUNXI_UART0_BAUDRATE, &console); 84 85 #ifdef BL32_BASE 86 /* Populate entry point information for BL32 */ 87 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 88 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 89 bl32_image_ep_info.pc = BL32_BASE; 90 #endif 91 92 /* Populate entry point information for BL33 */ 93 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 94 /* 95 * Tell BL31 where the non-trusted software image 96 * is located and the entry state information 97 */ 98 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 99 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 100 DISABLE_ALL_EXCEPTIONS); 101 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 102 103 /* Turn off all secondary CPUs */ 104 sunxi_disable_secondary_cpus(plat_my_core_pos()); 105 } 106 107 void bl31_plat_arch_setup(void) 108 { 109 sunxi_configure_mmu_el3(0); 110 } 111 112 void bl31_platform_setup(void) 113 { 114 const char *soc_name; 115 uint16_t soc_id = sunxi_read_soc_id(); 116 void *fdt; 117 118 switch (soc_id) { 119 case SUNXI_SOC_A64: 120 soc_name = "A64/H64/R18"; 121 break; 122 case SUNXI_SOC_H5: 123 soc_name = "H5"; 124 break; 125 case SUNXI_SOC_H6: 126 soc_name = "H6"; 127 break; 128 default: 129 soc_name = "unknown"; 130 break; 131 } 132 NOTICE("BL31: Detected Allwinner %s SoC (%04x)\n", soc_name, soc_id); 133 134 generic_delay_timer_init(); 135 136 fdt = sunxi_find_dtb(); 137 if (fdt) { 138 const char *model; 139 int length; 140 141 model = fdt_getprop(fdt, 0, "model", &length); 142 NOTICE("BL31: Found U-Boot DTB at %p, model: %s\n", fdt, 143 model ?: "unknown"); 144 } else { 145 NOTICE("BL31: No DTB found.\n"); 146 } 147 148 /* Configure the interrupt controller */ 149 gicv2_driver_init(&sunxi_gic_data); 150 gicv2_distif_init(); 151 gicv2_pcpu_distif_init(); 152 gicv2_cpuif_enable(); 153 154 sunxi_security_setup(); 155 156 /* 157 * On the A64 U-Boot's SPL sets the bus clocks to some conservative 158 * values, to work around FEL mode instabilities with SRAM C accesses. 159 * FEL mode is gone when we reach ATF, so bring the AHB1 bus 160 * (the "main" bus) clock frequency back to the recommended 200MHz, 161 * for improved performance. 162 */ 163 if (soc_id == SUNXI_SOC_A64) 164 mmio_write_32(SUNXI_CCU_BASE + 0x54, 0x00003180); 165 166 /* 167 * U-Boot or the kernel don't setup AHB2, which leaves it at the 168 * AHB1 frequency (200 MHz, see above). However Allwinner recommends 169 * 300 MHz, for improved Ethernet and USB performance. Switch the 170 * clock to use "PLL_PERIPH0 / 2". 171 */ 172 if (soc_id == SUNXI_SOC_A64 || soc_id == SUNXI_SOC_H5) 173 mmio_write_32(SUNXI_CCU_BASE + 0x5c, 0x1); 174 175 sunxi_pmic_setup(soc_id, fdt); 176 177 INFO("BL31: Platform setup done\n"); 178 } 179 180 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 181 { 182 assert(sec_state_is_valid(type) != 0); 183 184 if (type == NON_SECURE) 185 return &bl33_image_ep_info; 186 187 if ((type == SECURE) && bl32_image_ep_info.pc) 188 return &bl32_image_ep_info; 189 190 return NULL; 191 } 192