1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <common_def.h> 11 #include <sunxi_mmap.h> 12 #include <tbbr/tbbr_img_def.h> 13 14 #define BL31_BASE SUNXI_SRAM_A2_BASE 15 #define BL31_LIMIT (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE) 16 17 /* The traditional U-Boot load address is 160MB into DRAM, so at 0x4a000000 */ 18 #define PLAT_SUNXI_NS_IMAGE_OFFSET (SUNXI_DRAM_BASE + (160U << 20)) 19 20 #define CACHE_WRITEBACK_SHIFT 6 21 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 22 23 #define MAX_MMAP_REGIONS (4 + PLATFORM_MMAP_REGIONS) 24 #define MAX_XLAT_TABLES 2 25 26 #define PLAT_MAX_PWR_LVL_STATES 2 27 #define PLAT_MAX_RET_STATE 1 28 #define PLAT_MAX_OFF_STATE 2 29 30 #define PLAT_MAX_PWR_LVL 2 31 #define PLAT_NUM_PWR_DOMAINS (1 + \ 32 PLATFORM_CLUSTER_COUNT + \ 33 PLATFORM_CORE_COUNT) 34 35 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 36 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 37 38 #define PLATFORM_CLUSTER_COUNT 1 39 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 40 PLATFORM_MAX_CPUS_PER_CLUSTER) 41 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 42 #define PLATFORM_MMAP_REGIONS 3 43 #define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT) 44 45 #ifndef SPD_none 46 #ifndef BL32_BASE 47 #define BL32_BASE SUNXI_DRAM_BASE 48 #endif 49 #endif 50 51 #endif /* __PLATFORM_DEF_H__ */ 52