1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <common_def.h> 11 #include <sunxi_mmap.h> 12 #include <tbbr/tbbr_img_def.h> 13 #include <utils_def.h> 14 15 #define BL31_BASE SUNXI_SRAM_A2_BASE 16 #define BL31_LIMIT (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE) 17 18 /* The traditional U-Boot load address is 160MB into DRAM, so at 0x4a000000 */ 19 #define PLAT_SUNXI_NS_IMAGE_OFFSET (SUNXI_DRAM_BASE + (160U << 20)) 20 21 /* How much memory to reserve as secure for BL32, if configured */ 22 #define SUNXI_DRAM_SEC_SIZE (32U << 20) 23 24 /* How much DRAM to map (to map BL33, for fetching the DTB from U-Boot) */ 25 #define SUNXI_DRAM_MAP_SIZE (64U << 20) 26 27 #define CACHE_WRITEBACK_SHIFT 6 28 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 29 30 #define MAX_MMAP_REGIONS (3 + PLATFORM_MMAP_REGIONS) 31 #define MAX_XLAT_TABLES 1 32 33 #define PLAT_MAX_PWR_LVL_STATES U(2) 34 #define PLAT_MAX_RET_STATE U(1) 35 #define PLAT_MAX_OFF_STATE U(2) 36 37 #define PLAT_MAX_PWR_LVL U(2) 38 #define PLAT_NUM_PWR_DOMAINS (1 + \ 39 PLATFORM_CLUSTER_COUNT + \ 40 PLATFORM_CORE_COUNT) 41 42 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 43 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28) 44 45 #define PLATFORM_CLUSTER_COUNT 1 46 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 47 PLATFORM_MAX_CPUS_PER_CLUSTER) 48 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 49 #define PLATFORM_MMAP_REGIONS 4 50 #define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT) 51 52 #ifndef SPD_none 53 #ifndef BL32_BASE 54 #define BL32_BASE SUNXI_DRAM_BASE 55 #endif 56 #endif 57 58 #endif /* PLATFORM_DEF_H */ 59