1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <common_def.h> 11 #include <sunxi_mmap.h> 12 #include <tbbr/tbbr_img_def.h> 13 #include <utils_def.h> 14 15 #define BL31_BASE SUNXI_SRAM_A2_BASE 16 #define BL31_LIMIT (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE) 17 18 /* The traditional U-Boot load address is 160MB into DRAM, so at 0x4a000000 */ 19 #define PLAT_SUNXI_NS_IMAGE_OFFSET (SUNXI_DRAM_BASE + (160U << 20)) 20 21 #define CACHE_WRITEBACK_SHIFT 6 22 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 23 24 #define MAX_MMAP_REGIONS (4 + PLATFORM_MMAP_REGIONS) 25 #define MAX_XLAT_TABLES 2 26 27 #define PLAT_MAX_PWR_LVL_STATES U(2) 28 #define PLAT_MAX_RET_STATE U(1) 29 #define PLAT_MAX_OFF_STATE U(2) 30 31 #define PLAT_MAX_PWR_LVL U(2) 32 #define PLAT_NUM_PWR_DOMAINS (1 + \ 33 PLATFORM_CLUSTER_COUNT + \ 34 PLATFORM_CORE_COUNT) 35 36 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 37 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 38 39 #define PLATFORM_CLUSTER_COUNT 1 40 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 41 PLATFORM_MAX_CPUS_PER_CLUSTER) 42 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 43 #define PLATFORM_MMAP_REGIONS 3 44 #define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT) 45 46 #ifndef SPD_none 47 #ifndef BL32_BASE 48 #define BL32_BASE SUNXI_DRAM_BASE 49 #endif 50 #endif 51 52 #endif /* PLATFORM_DEF_H */ 53