1 /* 2 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <lib/utils_def.h> 12 #include <plat/common/common_def.h> 13 14 #include <sunxi_mmap.h> 15 16 #ifdef SUNXI_BL31_IN_DRAM 17 18 #define BL31_BASE SUNXI_DRAM_BASE 19 #define BL31_LIMIT (SUNXI_DRAM_BASE + 0x40000) 20 21 #define MAX_XLAT_TABLES 4 22 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 23 24 #define SUNXI_BL33_VIRT_BASE PRELOADED_BL33_BASE 25 26 #else /* !SUNXI_BL31_IN_DRAM */ 27 28 #define BL31_BASE (SUNXI_SRAM_A2_BASE + 0x4000) 29 #define BL31_LIMIT (SUNXI_SRAM_A2_BASE + \ 30 SUNXI_SRAM_A2_SIZE - SUNXI_SCP_SIZE) 31 32 /* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */ 33 #define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000) 34 #define BL31_NOBITS_LIMIT (SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE) 35 36 #define MAX_XLAT_TABLES 1 37 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28) 38 39 #define SUNXI_BL33_VIRT_BASE SUNXI_DRAM_VIRT_BASE 40 41 /* The SCP firmware is allocated the last 16KiB of SRAM A2. */ 42 #define SUNXI_SCP_BASE BL31_LIMIT 43 #define SUNXI_SCP_SIZE 0x4000 44 45 #endif /* SUNXI_BL31_IN_DRAM */ 46 47 /* How much DRAM to map (to map BL33, for fetching the DTB from U-Boot) */ 48 #define SUNXI_DRAM_MAP_SIZE (64U << 20) 49 50 #define CACHE_WRITEBACK_SHIFT 6 51 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 52 53 #define MAX_STATIC_MMAP_REGIONS 3 54 #define MAX_MMAP_REGIONS (5 + MAX_STATIC_MMAP_REGIONS) 55 56 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \ 57 (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200) 58 59 #define PLAT_MAX_PWR_LVL_STATES U(2) 60 #define PLAT_MAX_RET_STATE U(1) 61 #define PLAT_MAX_OFF_STATE U(2) 62 63 #define PLAT_MAX_PWR_LVL U(2) 64 #define PLAT_NUM_PWR_DOMAINS (U(1) + \ 65 PLATFORM_CLUSTER_COUNT + \ 66 PLATFORM_CORE_COUNT) 67 68 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 69 70 #define PLATFORM_CLUSTER_COUNT U(1) 71 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 72 PLATFORM_MAX_CPUS_PER_CLUSTER) 73 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 74 #define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT) 75 76 #ifndef SPD_none 77 #ifndef BL32_BASE 78 #define BL32_BASE SUNXI_DRAM_BASE 79 #endif 80 #endif 81 82 #endif /* PLATFORM_DEF_H */ 83