158032586SSamuel Holland /* 2ed306a86SSamuel Holland * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 358032586SSamuel Holland * 458032586SSamuel Holland * SPDX-License-Identifier: BSD-3-Clause 558032586SSamuel Holland */ 658032586SSamuel Holland 71083b2b3SAntonio Nino Diaz #ifndef PLATFORM_DEF_H 81083b2b3SAntonio Nino Diaz #define PLATFORM_DEF_H 958032586SSamuel Holland 1009d40e0eSAntonio Nino Diaz #include <common/tbbr/tbbr_img_def.h> 1109d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 1209d40e0eSAntonio Nino Diaz #include <plat/common/common_def.h> 1309d40e0eSAntonio Nino Diaz 1458032586SSamuel Holland #include <sunxi_mmap.h> 1558032586SSamuel Holland 16*ae3fe6e3SSamuel Holland #define BL31_BASE (SUNXI_SRAM_A2_BASE + 0x4000) 1758032586SSamuel Holland #define BL31_LIMIT (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE) 1858032586SSamuel Holland 19ed306a86SSamuel Holland /* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */ 20ed306a86SSamuel Holland #define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000) 21ed306a86SSamuel Holland #define BL31_NOBITS_LIMIT (SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE) 22ed306a86SSamuel Holland 2358032586SSamuel Holland /* The traditional U-Boot load address is 160MB into DRAM, so at 0x4a000000 */ 2458032586SSamuel Holland #define PLAT_SUNXI_NS_IMAGE_OFFSET (SUNXI_DRAM_BASE + (160U << 20)) 2558032586SSamuel Holland 26c3af6b00SAndre Przywara /* How much memory to reserve as secure for BL32, if configured */ 27c3af6b00SAndre Przywara #define SUNXI_DRAM_SEC_SIZE (32U << 20) 28c3af6b00SAndre Przywara 2941538930SAndre Przywara /* How much DRAM to map (to map BL33, for fetching the DTB from U-Boot) */ 30c3af6b00SAndre Przywara #define SUNXI_DRAM_MAP_SIZE (64U << 20) 31c3af6b00SAndre Przywara 3258032586SSamuel Holland #define CACHE_WRITEBACK_SHIFT 6 3358032586SSamuel Holland #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 3458032586SSamuel Holland 35ddb4c9e0SSamuel Holland #define MAX_MMAP_REGIONS (3 + PLATFORM_MMAP_REGIONS) 36c3af6b00SAndre Przywara #define MAX_XLAT_TABLES 1 3758032586SSamuel Holland 381083b2b3SAntonio Nino Diaz #define PLAT_MAX_PWR_LVL_STATES U(2) 391083b2b3SAntonio Nino Diaz #define PLAT_MAX_RET_STATE U(1) 401083b2b3SAntonio Nino Diaz #define PLAT_MAX_OFF_STATE U(2) 4158032586SSamuel Holland 421083b2b3SAntonio Nino Diaz #define PLAT_MAX_PWR_LVL U(2) 43e0b4cc75SDeepika Bhavnani #define PLAT_NUM_PWR_DOMAINS (U(1) + \ 4458032586SSamuel Holland PLATFORM_CLUSTER_COUNT + \ 4558032586SSamuel Holland PLATFORM_CORE_COUNT) 4658032586SSamuel Holland 4758032586SSamuel Holland #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 48c3af6b00SAndre Przywara #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28) 4958032586SSamuel Holland 50e0b4cc75SDeepika Bhavnani #define PLATFORM_CLUSTER_COUNT U(1) 5158032586SSamuel Holland #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 5258032586SSamuel Holland PLATFORM_MAX_CPUS_PER_CLUSTER) 53e0b4cc75SDeepika Bhavnani #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 54c3af6b00SAndre Przywara #define PLATFORM_MMAP_REGIONS 4 5558032586SSamuel Holland #define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT) 5658032586SSamuel Holland 57dab901f8SAmit Singh Tomar #ifndef SPD_none 58dab901f8SAmit Singh Tomar #ifndef BL32_BASE 59dab901f8SAmit Singh Tomar #define BL32_BASE SUNXI_DRAM_BASE 60dab901f8SAmit Singh Tomar #endif 61dab901f8SAmit Singh Tomar #endif 62dab901f8SAmit Singh Tomar 631083b2b3SAntonio Nino Diaz #endif /* PLATFORM_DEF_H */ 64