1*58032586SSamuel Holland /* 2*58032586SSamuel Holland * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3*58032586SSamuel Holland * 4*58032586SSamuel Holland * SPDX-License-Identifier: BSD-3-Clause 5*58032586SSamuel Holland */ 6*58032586SSamuel Holland 7*58032586SSamuel Holland #ifndef __PLATFORM_DEF_H__ 8*58032586SSamuel Holland #define __PLATFORM_DEF_H__ 9*58032586SSamuel Holland 10*58032586SSamuel Holland #include <common_def.h> 11*58032586SSamuel Holland #include <sunxi_mmap.h> 12*58032586SSamuel Holland #include <tbbr/tbbr_img_def.h> 13*58032586SSamuel Holland 14*58032586SSamuel Holland #define BL31_BASE SUNXI_SRAM_A2_BASE 15*58032586SSamuel Holland #define BL31_LIMIT (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE) 16*58032586SSamuel Holland 17*58032586SSamuel Holland /* The traditional U-Boot load address is 160MB into DRAM, so at 0x4a000000 */ 18*58032586SSamuel Holland #define PLAT_SUNXI_NS_IMAGE_OFFSET (SUNXI_DRAM_BASE + (160U << 20)) 19*58032586SSamuel Holland 20*58032586SSamuel Holland #define CACHE_WRITEBACK_SHIFT 6 21*58032586SSamuel Holland #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 22*58032586SSamuel Holland 23*58032586SSamuel Holland #define MAX_MMAP_REGIONS (4 + PLATFORM_MMAP_REGIONS) 24*58032586SSamuel Holland #define MAX_XLAT_TABLES 2 25*58032586SSamuel Holland 26*58032586SSamuel Holland #define PLAT_MAX_PWR_LVL_STATES 2 27*58032586SSamuel Holland #define PLAT_MAX_RET_STATE 1 28*58032586SSamuel Holland #define PLAT_MAX_OFF_STATE 2 29*58032586SSamuel Holland 30*58032586SSamuel Holland #define PLAT_MAX_PWR_LVL 2 31*58032586SSamuel Holland #define PLAT_NUM_PWR_DOMAINS (1 + \ 32*58032586SSamuel Holland PLATFORM_CLUSTER_COUNT + \ 33*58032586SSamuel Holland PLATFORM_CORE_COUNT) 34*58032586SSamuel Holland 35*58032586SSamuel Holland #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 36*58032586SSamuel Holland #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 37*58032586SSamuel Holland 38*58032586SSamuel Holland #define PLATFORM_CLUSTER_COUNT 1 39*58032586SSamuel Holland #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 40*58032586SSamuel Holland PLATFORM_MAX_CPUS_PER_CLUSTER) 41*58032586SSamuel Holland #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 42*58032586SSamuel Holland #define PLATFORM_MMAP_REGIONS 4 43*58032586SSamuel Holland #define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT) 44*58032586SSamuel Holland 45*58032586SSamuel Holland #endif /* __PLATFORM_DEF_H__ */ 46