158032586SSamuel Holland /* 2ed306a86SSamuel Holland * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 358032586SSamuel Holland * 458032586SSamuel Holland * SPDX-License-Identifier: BSD-3-Clause 558032586SSamuel Holland */ 658032586SSamuel Holland 71083b2b3SAntonio Nino Diaz #ifndef PLATFORM_DEF_H 81083b2b3SAntonio Nino Diaz #define PLATFORM_DEF_H 958032586SSamuel Holland 1009d40e0eSAntonio Nino Diaz #include <common/tbbr/tbbr_img_def.h> 1109d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 1209d40e0eSAntonio Nino Diaz #include <plat/common/common_def.h> 1309d40e0eSAntonio Nino Diaz 1458032586SSamuel Holland #include <sunxi_mmap.h> 1558032586SSamuel Holland 16ae3fe6e3SSamuel Holland #define BL31_BASE (SUNXI_SRAM_A2_BASE + 0x4000) 17*57b36632SSamuel Holland #define BL31_LIMIT (SUNXI_SRAM_A2_BASE + \ 18*57b36632SSamuel Holland SUNXI_SRAM_A2_SIZE - SUNXI_SCP_SIZE) 19*57b36632SSamuel Holland 20*57b36632SSamuel Holland /* The SCP firmware is allocated the last 16KiB of SRAM A2. */ 21*57b36632SSamuel Holland #define SUNXI_SCP_BASE BL31_LIMIT 22*57b36632SSamuel Holland #define SUNXI_SCP_SIZE 0x4000 2358032586SSamuel Holland 24ed306a86SSamuel Holland /* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */ 25ed306a86SSamuel Holland #define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000) 26ed306a86SSamuel Holland #define BL31_NOBITS_LIMIT (SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE) 27ed306a86SSamuel Holland 2858032586SSamuel Holland /* The traditional U-Boot load address is 160MB into DRAM, so at 0x4a000000 */ 2958032586SSamuel Holland #define PLAT_SUNXI_NS_IMAGE_OFFSET (SUNXI_DRAM_BASE + (160U << 20)) 3058032586SSamuel Holland 31c3af6b00SAndre Przywara /* How much memory to reserve as secure for BL32, if configured */ 32c3af6b00SAndre Przywara #define SUNXI_DRAM_SEC_SIZE (32U << 20) 33c3af6b00SAndre Przywara 3441538930SAndre Przywara /* How much DRAM to map (to map BL33, for fetching the DTB from U-Boot) */ 35c3af6b00SAndre Przywara #define SUNXI_DRAM_MAP_SIZE (64U << 20) 36c3af6b00SAndre Przywara 3758032586SSamuel Holland #define CACHE_WRITEBACK_SHIFT 6 3858032586SSamuel Holland #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 3958032586SSamuel Holland 40ddb4c9e0SSamuel Holland #define MAX_MMAP_REGIONS (3 + PLATFORM_MMAP_REGIONS) 41c3af6b00SAndre Przywara #define MAX_XLAT_TABLES 1 4258032586SSamuel Holland 431083b2b3SAntonio Nino Diaz #define PLAT_MAX_PWR_LVL_STATES U(2) 441083b2b3SAntonio Nino Diaz #define PLAT_MAX_RET_STATE U(1) 451083b2b3SAntonio Nino Diaz #define PLAT_MAX_OFF_STATE U(2) 4658032586SSamuel Holland 471083b2b3SAntonio Nino Diaz #define PLAT_MAX_PWR_LVL U(2) 48e0b4cc75SDeepika Bhavnani #define PLAT_NUM_PWR_DOMAINS (U(1) + \ 4958032586SSamuel Holland PLATFORM_CLUSTER_COUNT + \ 5058032586SSamuel Holland PLATFORM_CORE_COUNT) 5158032586SSamuel Holland 5258032586SSamuel Holland #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 53c3af6b00SAndre Przywara #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28) 5458032586SSamuel Holland 55e0b4cc75SDeepika Bhavnani #define PLATFORM_CLUSTER_COUNT U(1) 5658032586SSamuel Holland #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 5758032586SSamuel Holland PLATFORM_MAX_CPUS_PER_CLUSTER) 58e0b4cc75SDeepika Bhavnani #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 59*57b36632SSamuel Holland #define PLATFORM_MMAP_REGIONS 5 6058032586SSamuel Holland #define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT) 6158032586SSamuel Holland 62dab901f8SAmit Singh Tomar #ifndef SPD_none 63dab901f8SAmit Singh Tomar #ifndef BL32_BASE 64dab901f8SAmit Singh Tomar #define BL32_BASE SUNXI_DRAM_BASE 65dab901f8SAmit Singh Tomar #endif 66dab901f8SAmit Singh Tomar #endif 67dab901f8SAmit Singh Tomar 681083b2b3SAntonio Nino Diaz #endif /* PLATFORM_DEF_H */ 69