158032586SSamuel Holland /* 258032586SSamuel Holland * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 358032586SSamuel Holland * 458032586SSamuel Holland * SPDX-License-Identifier: BSD-3-Clause 558032586SSamuel Holland */ 658032586SSamuel Holland 71083b2b3SAntonio Nino Diaz #ifndef PLATFORM_DEF_H 81083b2b3SAntonio Nino Diaz #define PLATFORM_DEF_H 958032586SSamuel Holland 1058032586SSamuel Holland #include <common_def.h> 1158032586SSamuel Holland #include <sunxi_mmap.h> 1258032586SSamuel Holland #include <tbbr/tbbr_img_def.h> 131083b2b3SAntonio Nino Diaz #include <utils_def.h> 1458032586SSamuel Holland 1558032586SSamuel Holland #define BL31_BASE SUNXI_SRAM_A2_BASE 1658032586SSamuel Holland #define BL31_LIMIT (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE) 1758032586SSamuel Holland 1858032586SSamuel Holland /* The traditional U-Boot load address is 160MB into DRAM, so at 0x4a000000 */ 1958032586SSamuel Holland #define PLAT_SUNXI_NS_IMAGE_OFFSET (SUNXI_DRAM_BASE + (160U << 20)) 2058032586SSamuel Holland 21c3af6b00SAndre Przywara /* How much memory to reserve as secure for BL32, if configured */ 22c3af6b00SAndre Przywara #define SUNXI_DRAM_SEC_SIZE (32U << 20) 23c3af6b00SAndre Przywara 24c3af6b00SAndre Przywara /* How much DRAM to map */ 25c3af6b00SAndre Przywara #define SUNXI_DRAM_MAP_SIZE (64U << 20) 26c3af6b00SAndre Przywara 2758032586SSamuel Holland #define CACHE_WRITEBACK_SHIFT 6 2858032586SSamuel Holland #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 2958032586SSamuel Holland 30*43060513SAndre Przywara #define MAX_MMAP_REGIONS (3 + PLATFORM_MMAP_REGIONS) 31c3af6b00SAndre Przywara #define MAX_XLAT_TABLES 1 3258032586SSamuel Holland 331083b2b3SAntonio Nino Diaz #define PLAT_MAX_PWR_LVL_STATES U(2) 341083b2b3SAntonio Nino Diaz #define PLAT_MAX_RET_STATE U(1) 351083b2b3SAntonio Nino Diaz #define PLAT_MAX_OFF_STATE U(2) 3658032586SSamuel Holland 371083b2b3SAntonio Nino Diaz #define PLAT_MAX_PWR_LVL U(2) 3858032586SSamuel Holland #define PLAT_NUM_PWR_DOMAINS (1 + \ 3958032586SSamuel Holland PLATFORM_CLUSTER_COUNT + \ 4058032586SSamuel Holland PLATFORM_CORE_COUNT) 4158032586SSamuel Holland 4258032586SSamuel Holland #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 43c3af6b00SAndre Przywara #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28) 4458032586SSamuel Holland 4558032586SSamuel Holland #define PLATFORM_CLUSTER_COUNT 1 4658032586SSamuel Holland #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 4758032586SSamuel Holland PLATFORM_MAX_CPUS_PER_CLUSTER) 4858032586SSamuel Holland #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 49c3af6b00SAndre Przywara #define PLATFORM_MMAP_REGIONS 4 5058032586SSamuel Holland #define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT) 5158032586SSamuel Holland 52dab901f8SAmit Singh Tomar #ifndef SPD_none 53dab901f8SAmit Singh Tomar #ifndef BL32_BASE 54dab901f8SAmit Singh Tomar #define BL32_BASE SUNXI_DRAM_BASE 55dab901f8SAmit Singh Tomar #endif 56dab901f8SAmit Singh Tomar #endif 57dab901f8SAmit Singh Tomar 581083b2b3SAntonio Nino Diaz #endif /* PLATFORM_DEF_H */ 59