158032586SSamuel Holland /* 2ed306a86SSamuel Holland * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 358032586SSamuel Holland * 458032586SSamuel Holland * SPDX-License-Identifier: BSD-3-Clause 558032586SSamuel Holland */ 658032586SSamuel Holland 71083b2b3SAntonio Nino Diaz #ifndef PLATFORM_DEF_H 81083b2b3SAntonio Nino Diaz #define PLATFORM_DEF_H 958032586SSamuel Holland 1009d40e0eSAntonio Nino Diaz #include <common/tbbr/tbbr_img_def.h> 1109d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 1209d40e0eSAntonio Nino Diaz #include <plat/common/common_def.h> 1309d40e0eSAntonio Nino Diaz 1458032586SSamuel Holland #include <sunxi_mmap.h> 1558032586SSamuel Holland 16*01cec8f4SAndre Przywara /* The SCP firmware is allocated the last 16KiB of SRAM A2. */ 17*01cec8f4SAndre Przywara #define SUNXI_SCP_SIZE 0x4000 18*01cec8f4SAndre Przywara 19*01cec8f4SAndre Przywara #ifdef SUNXI_BL31_IN_DRAM 20*01cec8f4SAndre Przywara #else /* !SUNXI_BL31_IN_DRAM */ 21*01cec8f4SAndre Przywara 22ae3fe6e3SSamuel Holland #define BL31_BASE (SUNXI_SRAM_A2_BASE + 0x4000) 2357b36632SSamuel Holland #define BL31_LIMIT (SUNXI_SRAM_A2_BASE + \ 2457b36632SSamuel Holland SUNXI_SRAM_A2_SIZE - SUNXI_SCP_SIZE) 2557b36632SSamuel Holland #define SUNXI_SCP_BASE BL31_LIMIT 2658032586SSamuel Holland 27ed306a86SSamuel Holland /* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */ 28ed306a86SSamuel Holland #define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000) 29ed306a86SSamuel Holland #define BL31_NOBITS_LIMIT (SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE) 30ed306a86SSamuel Holland 31*01cec8f4SAndre Przywara #define MAX_XLAT_TABLES 1 32*01cec8f4SAndre Przywara #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28) 33*01cec8f4SAndre Przywara #define SUNXI_BL33_VIRT_BASE (SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE) 34*01cec8f4SAndre Przywara 35*01cec8f4SAndre Przywara #endif /* SUNXI_BL31_IN_DRAM */ 36*01cec8f4SAndre Przywara 37c3af6b00SAndre Przywara /* How much memory to reserve as secure for BL32, if configured */ 38c3af6b00SAndre Przywara #define SUNXI_DRAM_SEC_SIZE (32U << 20) 39c3af6b00SAndre Przywara 4041538930SAndre Przywara /* How much DRAM to map (to map BL33, for fetching the DTB from U-Boot) */ 41c3af6b00SAndre Przywara #define SUNXI_DRAM_MAP_SIZE (64U << 20) 42c3af6b00SAndre Przywara 4358032586SSamuel Holland #define CACHE_WRITEBACK_SHIFT 6 4458032586SSamuel Holland #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 4558032586SSamuel Holland 46ddb4c9e0SSamuel Holland #define MAX_MMAP_REGIONS (3 + PLATFORM_MMAP_REGIONS) 4758032586SSamuel Holland 48e382c88eSSamuel Holland #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \ 49e382c88eSSamuel Holland (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200) 50e382c88eSSamuel Holland 511083b2b3SAntonio Nino Diaz #define PLAT_MAX_PWR_LVL_STATES U(2) 521083b2b3SAntonio Nino Diaz #define PLAT_MAX_RET_STATE U(1) 531083b2b3SAntonio Nino Diaz #define PLAT_MAX_OFF_STATE U(2) 5458032586SSamuel Holland 551083b2b3SAntonio Nino Diaz #define PLAT_MAX_PWR_LVL U(2) 56e0b4cc75SDeepika Bhavnani #define PLAT_NUM_PWR_DOMAINS (U(1) + \ 5758032586SSamuel Holland PLATFORM_CLUSTER_COUNT + \ 5858032586SSamuel Holland PLATFORM_CORE_COUNT) 5958032586SSamuel Holland 6058032586SSamuel Holland #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 6158032586SSamuel Holland 62e0b4cc75SDeepika Bhavnani #define PLATFORM_CLUSTER_COUNT U(1) 6358032586SSamuel Holland #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 6458032586SSamuel Holland PLATFORM_MAX_CPUS_PER_CLUSTER) 65e0b4cc75SDeepika Bhavnani #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 6657b36632SSamuel Holland #define PLATFORM_MMAP_REGIONS 5 6758032586SSamuel Holland #define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT) 6858032586SSamuel Holland 69dab901f8SAmit Singh Tomar #ifndef SPD_none 70dab901f8SAmit Singh Tomar #ifndef BL32_BASE 71dab901f8SAmit Singh Tomar #define BL32_BASE SUNXI_DRAM_BASE 72dab901f8SAmit Singh Tomar #endif 73dab901f8SAmit Singh Tomar #endif 74dab901f8SAmit Singh Tomar 751083b2b3SAntonio Nino Diaz #endif /* PLATFORM_DEF_H */ 76