1a80490c5SAndre Przywara# 2fb23b104SSamuel Holland# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3a80490c5SAndre Przywara# 4a80490c5SAndre Przywara# SPDX-License-Identifier: BSD-3-Clause 5a80490c5SAndre Przywara# 6a80490c5SAndre Przywara 7a80490c5SAndre Przywarainclude lib/xlat_tables_v2/xlat_tables.mk 8a80490c5SAndre Przywara 9a80490c5SAndre PrzywaraAW_PLAT := plat/allwinner 10a80490c5SAndre Przywara 11252c1d1dSSamuel HollandPLAT_INCLUDES := -Iinclude/plat/arm/common/aarch64 \ 12a80490c5SAndre Przywara -I${AW_PLAT}/common/include \ 13a80490c5SAndre Przywara -I${AW_PLAT}/${PLAT}/include 14a80490c5SAndre Przywara 1541538930SAndre Przywarainclude lib/libfdt/libfdt.mk 1641538930SAndre Przywara 17985ee0b7SJulius WernerPLAT_BL_COMMON_SOURCES := drivers/ti/uart/${ARCH}/16550_console.S \ 18a80490c5SAndre Przywara ${XLAT_TABLES_LIB_SRCS} \ 19a80490c5SAndre Przywara ${AW_PLAT}/common/plat_helpers.S \ 20a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_common.c 21a80490c5SAndre Przywara 22fb23b104SSamuel HollandBL31_SOURCES += drivers/allwinner/axp/common.c \ 2350cabf6dSSamuel Holland drivers/allwinner/sunxi_msgbox.c \ 24*e382c88eSSamuel Holland drivers/arm/css/scpi/css_scpi.c \ 25fb23b104SSamuel Holland drivers/arm/gic/common/gic_common.c \ 26a80490c5SAndre Przywara drivers/arm/gic/v2/gicv2_helpers.c \ 27a80490c5SAndre Przywara drivers/arm/gic/v2/gicv2_main.c \ 28a80490c5SAndre Przywara drivers/delay_timer/delay_timer.c \ 29a80490c5SAndre Przywara drivers/delay_timer/generic_delay_timer.c \ 30a80490c5SAndre Przywara lib/cpus/${ARCH}/cortex_a53.S \ 31a80490c5SAndre Przywara plat/common/plat_gicv2.c \ 32a80490c5SAndre Przywara plat/common/plat_psci_common.c \ 33a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_bl31_setup.c \ 34a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_cpu_ops.c \ 35a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_pm.c \ 36a80490c5SAndre Przywara ${AW_PLAT}/${PLAT}/sunxi_power.c \ 37a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_security.c \ 38a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_topology.c 39a80490c5SAndre Przywara 40a80490c5SAndre Przywara# The bootloader is guaranteed to only run on CPU 0 by the boot ROM. 41a80490c5SAndre PrzywaraCOLD_BOOT_SINGLE_CPU := 1 42a80490c5SAndre Przywara 438f31853bSSamuel Holland# Do not enable SPE (not supported on ARM v8.0). 448f31853bSSamuel HollandENABLE_SPE_FOR_LOWER_ELS := 0 458f31853bSSamuel Holland 468f31853bSSamuel Holland# Do not enable SVE (not supported on ARM v8.0). 478f31853bSSamuel HollandENABLE_SVE_FOR_NS := 0 488f31853bSSamuel Holland 49a80490c5SAndre Przywara# Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4. 50a80490c5SAndre PrzywaraERRATA_A53_835769 := 1 51a80490c5SAndre PrzywaraERRATA_A53_843419 := 1 52a80490c5SAndre PrzywaraERRATA_A53_855873 := 1 53a80490c5SAndre Przywara 54a80490c5SAndre Przywara# The reset vector can be changed for each CPU. 55a80490c5SAndre PrzywaraPROGRAMMABLE_RESET_ADDRESS := 1 56a80490c5SAndre Przywara 57a80490c5SAndre Przywara# Allow mapping read-only data as execute-never. 58a80490c5SAndre PrzywaraSEPARATE_CODE_AND_RODATA := 1 59a80490c5SAndre Przywara 60ed306a86SSamuel Holland# Put NOBITS memory in SRAM A1, overwriting U-Boot's SPL. 61ed306a86SSamuel HollandSEPARATE_NOBITS_REGION := 1 62ed306a86SSamuel Holland 63a80490c5SAndre Przywara# BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL 64a80490c5SAndre PrzywaraRESET_TO_BL31 := 1 6543060513SAndre Przywara 668f31853bSSamuel Holland# This platform is single-cluster and does not require coherency setup. 678f31853bSSamuel HollandWARMBOOT_ENABLE_DCACHE_EARLY := 1 68