1*a80490c5SAndre Przywara# 2*a80490c5SAndre Przywara# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3*a80490c5SAndre Przywara# 4*a80490c5SAndre Przywara# SPDX-License-Identifier: BSD-3-Clause 5*a80490c5SAndre Przywara# 6*a80490c5SAndre Przywara 7*a80490c5SAndre Przywarainclude lib/xlat_tables_v2/xlat_tables.mk 8*a80490c5SAndre Przywara 9*a80490c5SAndre PrzywaraAW_PLAT := plat/allwinner 10*a80490c5SAndre Przywara 11*a80490c5SAndre PrzywaraPLAT_INCLUDES := -Iinclude/plat/arm/common \ 12*a80490c5SAndre Przywara -Iinclude/plat/arm/common/aarch64 \ 13*a80490c5SAndre Przywara -I${AW_PLAT}/common/include \ 14*a80490c5SAndre Przywara -I${AW_PLAT}/${PLAT}/include 15*a80490c5SAndre Przywara 16*a80490c5SAndre PrzywaraPLAT_BL_COMMON_SOURCES := drivers/console/${ARCH}/console.S \ 17*a80490c5SAndre Przywara drivers/ti/uart/${ARCH}/16550_console.S \ 18*a80490c5SAndre Przywara ${XLAT_TABLES_LIB_SRCS} \ 19*a80490c5SAndre Przywara ${AW_PLAT}/common/plat_helpers.S \ 20*a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_common.c 21*a80490c5SAndre Przywara 22*a80490c5SAndre PrzywaraBL31_SOURCES += drivers/arm/gic/common/gic_common.c \ 23*a80490c5SAndre Przywara drivers/arm/gic/v2/gicv2_helpers.c \ 24*a80490c5SAndre Przywara drivers/arm/gic/v2/gicv2_main.c \ 25*a80490c5SAndre Przywara drivers/delay_timer/delay_timer.c \ 26*a80490c5SAndre Przywara drivers/delay_timer/generic_delay_timer.c \ 27*a80490c5SAndre Przywara lib/cpus/${ARCH}/cortex_a53.S \ 28*a80490c5SAndre Przywara plat/common/plat_gicv2.c \ 29*a80490c5SAndre Przywara plat/common/plat_psci_common.c \ 30*a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_bl31_setup.c \ 31*a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_cpu_ops.c \ 32*a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_pm.c \ 33*a80490c5SAndre Przywara ${AW_PLAT}/${PLAT}/sunxi_power.c \ 34*a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_security.c \ 35*a80490c5SAndre Przywara ${AW_PLAT}/common/sunxi_topology.c 36*a80490c5SAndre Przywara 37*a80490c5SAndre Przywara# The bootloader is guaranteed to only run on CPU 0 by the boot ROM. 38*a80490c5SAndre PrzywaraCOLD_BOOT_SINGLE_CPU := 1 39*a80490c5SAndre Przywara 40*a80490c5SAndre Przywara# Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4. 41*a80490c5SAndre PrzywaraERRATA_A53_835769 := 1 42*a80490c5SAndre PrzywaraERRATA_A53_843419 := 1 43*a80490c5SAndre PrzywaraERRATA_A53_855873 := 1 44*a80490c5SAndre Przywara 45*a80490c5SAndre PrzywaraMULTI_CONSOLE_API := 1 46*a80490c5SAndre Przywara 47*a80490c5SAndre Przywara# The reset vector can be changed for each CPU. 48*a80490c5SAndre PrzywaraPROGRAMMABLE_RESET_ADDRESS := 1 49*a80490c5SAndre Przywara 50*a80490c5SAndre Przywara# Allow mapping read-only data as execute-never. 51*a80490c5SAndre PrzywaraSEPARATE_CODE_AND_RODATA := 1 52*a80490c5SAndre Przywara 53*a80490c5SAndre Przywara# BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL 54*a80490c5SAndre PrzywaraRESET_TO_BL31 := 1 55